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An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process.
Karthik Rajagopal
Aatmesh
Vinod Menezes
Published in:
ISQED (2009)
Keyphrases
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low voltage
high speed
design considerations
low power
leakage current
wireless sensor networks
digital images
power management
cmos technology
power line