Login / Signup
A high performance, high voltage output buffer in a low voltage CMOS process.
Rajat Chauhan
Karthik Rajagopal
Vinod Menezes
H. M. Roopashree
Sanish Koshy Jacob
Published in:
CICC (2005)
Keyphrases
</>
high voltage
low voltage
power line
design considerations
operating conditions
normal operation
partial discharge
random access memory
cost effective
input data
cmos technology
artificial neural networks
high speed