Subash Chandar G.

Publication Activity (10 Years)

Years Active: 1999-2006
Publications (10 Years): 0

Publications

Subash Chandar G., Mahesh Mehendale, R. Govindarajan
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. J. VLSI Signal Process. 44 (3) (2006)
Soujanna Sarkar, Subash Chandar G., Sanjay Shinde
Effective IP reuse for high quality SOC design. SoCC (2005)
Soujanna Sarkar, Sanjay Shinde, Subash Chandar G.
An Effective IP Reuse Methodology for Quality System-on-Chip Design. SoC (2005)
Soujanna Sarkar, Subash Chandar G.
An Effective Framework for Enabling the Reuse of External Soft IP. DSD (2005)
Subrangshu Das, Subash Chandar G., Ashutosh Tiwari
Reset Careabouts in a SoC Design. VLSI Design (2004)
Subash Chandar G., S. Vaideeswaran
Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. ASP-DAC (2001)
Subash Chandar G., Mahesh Mehendale, R. Govindarajan
Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. ICCAD (2001)
Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. VLSI Design (2000)
Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ICCD (1999)