Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers.
Subash Chandar G.S. VaideeswaranPublished in: ASP-DAC (2001)
Keyphrases
- multi core processors
- functional verification
- processor core
- parallel architectures
- model checking
- multicore processors
- high speed
- multi core systems
- parallel processing
- database workloads
- level parallelism
- parallel architecture
- dynamic random access memory
- general purpose processors
- real time
- signature verification
- distributed memory
- computing power
- computer architecture
- database systems
- data sets