Jagdish C. Rao

Publication Activity (10 Years)

Years Active: 1999-2009
Publications (10 Years): 0

Publications

R. Venkatraman, Shrikrishna Pundoor, Arun Koithyar, Madhusudan Rao, Jagdish C. Rao
Optimisation Quality Assessment in Large, Complex SoC Designs Challenges and Solutions. VLSI Design (2009)
Jithendra Srinivas, Madhusudan Rao, Sukumar Jairam, H. Udayakumar, Jagdish C. Rao
Clock gating effectiveness metrics: Applications to power optimization. ISQED (2009)
Sukumar Jairam, Madhusudan Rao, Jithendra Srinivas, Parimala Vishwanath, H. Udayakumar, Jagdish C. Rao
Clock gating for power optimization in ASIC design cycle theory & practice. ISLPED (2008)
Bhaskar J. Karmakar, V. Kalyana Chakravarty, R. Venkatraman, Jagdish C. Rao
Enabling Quality and Schedule Predictability in SoC Design using HandoffQC. ISQED (2006)
Karanth Shankaranarayana, Soujanna Sarkar, R. Venkatraman, Shyam S. Jagini, N. Venkatesh, Jagdish C. Rao, H. Udayakumar, M. Sambandam, K. P. Sheshadri, S. Talapatra, Parag Mhatre, Jais Abraham, Rubin A. Parekhji
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon. VLSI Design (2002)
Karthikeyan Madathil, Jagdish C. Rao, Subash Chandar G., Amitabh Menon, Avinash K. Gautam, Amit M. Brahme, H. Udayakumar
A Framework for Cost vs. Performance Tradeoffs in the Design of Digital Signal Processor Cores. VLSI Design (2000)
Avinash K. Gautam, Jagdish C. Rao, Karthikeyan Madathil, Vilesh Shah, H. Udayakumar, Amitabh Menon, Subash Chandar G.
A Design Methodology for a Fully Synthesized High Speed DSP Core in a Deep Sub-Micron Technology. ICCD (1999)
Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. VLSI Design (1999)