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Clock gating for power optimization in ASIC design cycle theory & practice.
Sukumar Jairam
Madhusudan Rao
Jithendra Srinivas
Parimala Vishwanath
H. Udayakumar
Jagdish C. Rao
Published in:
ISLPED (2008)
Keyphrases
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power consumption
design methodology
power reduction
power dissipation
case study
design process
user interface
hidden markov models
circuit design
formal verification
hardware architecture
power management
power saving
clock gating