Sunil D. Sherlekar

Publication Activity (10 Years)

Years Active: 1988-2012
Publications (10 Years): 0

Top Topics

Computer Architecture

Parallel Computing

Top Venues

Publications

Sunil D. Sherlekar
Parallel Computing Goes Mainstream. IC3 (2012)
Sunil D. Sherlekar
Intel Many Integrated Core (MIC) Architecture. ICPADS (2012)
Sunil D. Sherlekar, Rajeev Prasad
A Global Access Independent Billing Model: Users' Perspective. Wirel. Pers. Commun. 26 (2-3) (2003)
Mahesh Mehendale, Sunil D. Sherlekar
Power Reduction Techniques for Portable DSP Applications. VLSI Design (2000)
Mahesh Mehendale, Sunil D. Sherlekar
Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design (1999)
Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design (1998)
Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Low-power realization of FIR filters on programmable DSPs. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design (1997)
Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar
Optimized Code Generation of Multiplication-free Linear Transforms. DAC (1996)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Low power realization of FIR filters using multirate architectures. VLSI Design (1996)
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electron. Test. 8 (2) (1996)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Techniques for low power realization for FIR filters. ASP-DAC (1995)
B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design (1995)
Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh
Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD (1995)
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
Concurrent Error Detection Using Monitoring Machines. IEEE Des. Test Comput. 12 (3) (1995)
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design (1993)
Sunil D. Sherlekar
Export of VLSI Design and CAD: Present and Future. VLSI Design (1993)
Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran
A Behavioral Fault Simulator for Ideal. IEEE Des. Test Comput. 9 (4) (1992)
Yogesh Mishra, Sunil D. Sherlekar, G. Venkatesh
Path breaker: a tool for the optimal design of speed independent asynchronous controllers. EURO-DAC (1992)
Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh
A Behavioral Fault Simulator For Ideal. VLSI Design (1992)
Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar
A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC (1991)
Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh
A methodology for the design of SFS/SCD circuits for a class of unordered codes. J. Electron. Test. 2 (3) (1991)
Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar
Ideas: a tool for VLSI CAD. IEEE Des. Test 6 (5) (1989)
Sunil D. Sherlekar, P. S. Subramanian
Conditionally robust two-pattern tests and CMOS design for testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (3) (1988)