John A. Waicukauski

Publication Activity (10 Years)

Years Active: 1981-2018
Publications (10 Years): 2

Top Topics

Abductive Reasoning

Text Compression

Compression Ratio

Test Generation

Top Venues

Publications

Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn
XLBIST: X-Tolerant Logic BIST. ITC (2018)
Emil Gizdarski, Peter Wohl, John A. Waicukauski
A New Paradigm for Synthesis of Linear Decompressors. DAC (2017)
Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane
Achieving extreme scan compression for SoC Designs. ITC (2014)
Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn
Two-level compression through selective reseeding. ITC (2013)
Peter Wohl, John A. Waicukauski
Improving test generation by use of majority gates. VTS (2013)
Peter Wohl, John A. Waicukauski, Jonathon E. Colburn
Enhancing testability by structured partial scan. VTS (2012)
Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn
Hybrid selector for high-X scan compression. ITC (2012)
X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath
Highly efficient parallel ATPG based on shared memory. ITC (2010)
Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski
Fully X-tolerant, very high scan compression. DAC (2010)
Peter Wohl, John A. Waicukauski, T. Finklea
Increasing PRPG-based compression by delayed justification. ITC (2010)
Peter Wohl, John A. Waicukauski, Frederic Neuveux
Increasing Scan Compression by Using X-chains. ITC (2008)
Peter Wohl, John A. Waicukauski, Sanjay Patel
Automated Design and Insertion of Optimal One-Hot Bus Encoders. VTS (2007)
Peter Wohl, John A. Waicukauski, Sanjay Ramnath
Fully X-tolerant combinational scan compression. ITC (2007)
Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
Minimizing the Impact of Scan Compression. VTS (2007)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
Efficient compression of deterministic patterns into multiple PRPG seeds. ITC (2005)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. VTS (2005)
Peter Wohl, John A. Waicukauski, Sanjay Patel
Scalable selector architecture for x-tolerant deterministic BIST. DAC (2004)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. ITC (2003)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
Efficient compression and application of deterministic patterns in a logic BIST architecture. DAC (2003)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston
Effective diagnostics through interval unloads in a BIST environment. DAC (2002)
Vishal Jain, John A. Waicukauski
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique. ITC (2002)
Peter Wohl, John A. Waicukauski, Thomas W. Williams
Design of compactors for signature-analyzers in built-in self-test. ITC (2001)
Peter Wohl, John A. Waicukauski
Optimizing the flattened test-generation model for very large designs. ITC (2000)
Peter Wohl, John A. Waicukauski
Using Verilog simulation libraries for ATPG. ITC (1999)
Peter Wohl, John A. Waicukauski
Defining ATPG rules checking in STIL. ITC (1998)
Peter Wohl, John A. Waicukauski
Extracting gate-level networks from simulation tables. ITC (1998)
Peter Wohl, John A. Waicukauski
A Unified Interface for Scan Test Generation Based on STIL. ITC (1997)
Peter Wohl, John A. Waicukauski
Using ATPG for clock rules checking in complex scan design. VTS (1997)
Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski
Two-Dimensional Test Data Decompressor for Multiple Scan Designs. ITC (1996)
Bejoy G. Oomman, Wu-Tung Cheng, John A. Waicukauski
A Universal Technique for Accelerating Simulation of Scan Test Patterns. ITC (1996)
Peter Wohl, John A. Waicukauski, Matthew Graf
Testing "untestable" faults in three-state circuits. VTS (1996)
Peter Wohl, John A. Waicukauski
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. ITC (1996)
Vijay S. Iyengar, Barry K. Rosen, John A. Waicukauski
On computing the sizes of detected delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9 (3) (1990)
John A. Waicukauski, Paul A. Shupe, David Giramma, Arshad Matin
ATPG for ultra-large structured designs. ITC (1990)
John A. Waicukauski, Eric Lindbloom, Edward B. Eichelberger, Orazio P. Forlenza
A Method for Generating Weighted Random Test Patterns. IBM J. Res. Dev. 33 (2) (1989)
John A. Waicukauski, Eric Lindbloom
Failure diagnosis of structured VLSI. IEEE Des. Test 6 (4) (1989)
Miron Abramovici, Balaji Krishnamurthy, Rob Mathews, Bill Rogers, Michael Schulz, Sharad Seth, John A. Waicukauski
What is the Path to Fast Fault Simulation? ITC (1988)
John A. Waicukauski, Eric Lindbloom
Fault Detection Effectiveness of Weighted Random Patterns. ITC (1988)
John A. Waicukauski, Eric Lindbloom, Barry K. Rosen, Vijay S. Iyengar
Transition Fault Simulation. IEEE Des. Test 4 (2) (1987)
John A. Waicukauski, Eric Lindbloom, Vijay S. Iyengar, Barry K. Rosen
Transition Fault Simulation by Parallel Pattern Single Fault Propagation. ITC (1986)
John A. Waicukauski, Eric Lindbloom, Edward B. Eichelberger, Donato O. Forlenza, Tim McCarthy
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation. ITC (1985)
Franco Motika, John A. Waicukauski, Edward B. Eichelberger, Eric Lindbloom
An LSSD Pseudo Random Pattern Test System. ITC (1983)
Y. Arzoumanian, John A. Waicukauski
Fault Diagnosis in an LSSD Environment. ITC (1981)