Peter Wohl

Publication Activity (10 Years)

Years Active: 1990-2018
Publications (10 Years): 2

Top Topics

Compression Rate

Abductive Reasoning

Text Compression

Test Generation

Top Venues

Publications

Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn
XLBIST: X-Tolerant Logic BIST. ITC (2018)
Emil Gizdarski, Peter Wohl, John A. Waicukauski
A New Paradigm for Synthesis of Linear Decompressors. DAC (2017)
X. Cai, Peter Wohl, Daniel Martin
Fault sharing in a copy-on-write based ATPG system. ITC (2014)
Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane
Achieving extreme scan compression for SoC Designs. ITC (2014)
Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn
Two-level compression through selective reseeding. ITC (2013)
Peter Wohl, John A. Waicukauski
Improving test generation by use of majority gates. VTS (2013)
X. Cai, Peter Wohl
A distributed-multicore hybrid ATPG system. ITC (2013)
Peter Wohl, John A. Waicukauski, Jonathon E. Colburn
Enhancing testability by structured partial scan. VTS (2012)
Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn
Hybrid selector for high-X scan compression. ITC (2012)
X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath
Highly efficient parallel ATPG based on shared memory. ITC (2010)
Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski
Fully X-tolerant, very high scan compression. DAC (2010)
Peter Wohl, John A. Waicukauski, T. Finklea
Increasing PRPG-based compression by delayed justification. ITC (2010)
Peter Wohl, John A. Waicukauski, Frederic Neuveux
Increasing Scan Compression by Using X-chains. ITC (2008)
Peter Wohl, John A. Waicukauski, Sanjay Patel
Automated Design and Insertion of Optimal One-Hot Bus Encoders. VTS (2007)
Peter Wohl, John A. Waicukauski, Sanjay Ramnath
Fully X-tolerant combinational scan compression. ITC (2007)
Rohit Kapur, T. Finklea, Felix Ng, Anshuman Chandra, Sanjay Ramnath, Peter Wohl, Thomas W. Williams, Ashok Anbalan, Sandeep S. Kulkarni, Tammy Fernandes, Pramod Notiyath, Rajesh Uppuluri
DFT MAX and Power. J. Low Power Electron. 3 (2) (2007)
Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini
Minimizing the Impact of Scan Compression. VTS (2007)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur
Efficient compression of deterministic patterns into multiple PRPG seeds. ITC (2005)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. VTS (2005)
Peter Wohl, John A. Waicukauski, Sanjay Patel
Scalable selector architecture for x-tolerant deterministic BIST. DAC (2004)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. ITC (2003)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin
Efficient compression and application of deterministic patterns in a logic BIST architecture. DAC (2003)
Peter Wohl, Leendert M. Huisman
Analysis and Design of Optimal Combinational Compactors. VTS (2003)
Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston
Effective diagnostics through interval unloads in a BIST environment. DAC (2002)
Peter Wohl, John A. Waicukauski, Thomas W. Williams
Design of compactors for signature-analyzers in built-in self-test. ITC (2001)
Peter Wohl, John A. Waicukauski
Optimizing the flattened test-generation model for very large designs. ITC (2000)
Peter Wohl, Nathan Biggs
P1450.1: STIL for the Simulation Environmen. VTS (2000)
Peter Wohl
Output in still, input in still. ITC (1999)
Peter Wohl, John A. Waicukauski
Using Verilog simulation libraries for ATPG. ITC (1999)
Peter Wohl, John A. Waicukauski
Defining ATPG rules checking in STIL. ITC (1998)
Peter Wohl, John A. Waicukauski
Extracting gate-level networks from simulation tables. ITC (1998)
Peter Wohl, John A. Waicukauski
A Unified Interface for Scan Test Generation Based on STIL. ITC (1997)
Peter Wohl, John A. Waicukauski
Using ATPG for clock rules checking in complex scan design. VTS (1997)
Peter Wohl, John A. Waicukauski, Matthew Graf
Testing "untestable" faults in three-state circuits. VTS (1996)
Peter Wohl, John A. Waicukauski
Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. ITC (1996)
Peter Wohl
Efficiency through Reduced Communication in Message Passing Simulation of Neural Networks. Int. J. Artif. Intell. Tools 2 (1) (1993)
Peter Wohl, Thomas W. Christopher
Designing Conceptual Clustering for Parallel Implementation. ICPP (3) (1992)
Peter Wohl, Thomas W. Christopher
Parallel Conceptual Clustering through Message-Driven Computing. ICPP (2) (1991)
Peter Wohl, Thomas W. Christopher
A Parallel Processing Approach to Incremental Conceptual Clustering. IPPS (1991)
Peter Wohl, Thomas W. Christopher
MIMD implementation of neural networks through pipelined, parallel communication trees. ICTAI (1991)
Peter Wohl, Thomas W. Christopher
SIMD Neural Net Mapping on MIMD Architectures. ICPP (1) (1990)