Leendert M. Huisman

Publication Activity (10 Years)

Years Active: 1983-2004
Publications (10 Years): 0

Publications

Leendert M. Huisman
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Leendert M. Huisman, Maroun Kassab, Leah Pastel
Data Mining Integrated Circuit Fails with Fail Commonalities. ITC (2004)
Peter Wohl, Leendert M. Huisman
Analysis and Design of Optimal Combinational Compactors. VTS (2003)
Thomas Bartenstein, Douglas Heaberlin, Leendert M. Huisman, David Sliwinski
Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm. ITC (2001)
Daniel R. Knebel, Pia Sanda, Moyra K. McManus, Jeffrey A. Kash, James C. Tsang, David P. Vallett, Leendert M. Huisman, Phil Nigh, Rick Rizzolo, Peilin Song, Franco Motika
Diagnosis and characterization of timing-related defects by time-dependent light emission. ITC (1998)
Leendert M. Huisman
Correlations between path delays and the accuracy of performance prediction. ITC (1998)
Leendert M. Huisman
Yield fluctuations and defect models. J. Electron. Test. 7 (3) (1995)
Peter C. Maxwell, Robert C. Aitken, Leendert M. Huisman
The Effect on Quality of Non-Uniform Fault Coverage and Fault Probability. ITC (1994)
Leendert M. Huisman, Sandip Kundu
Highly Reliable Symmetric Networks. IEEE Trans. Parallel Distributed Syst. 5 (1) (1994)
Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy
A Small Test Generator for Large Designs. ITC (1992)
Sandip Kundu, Indira Nair, Leendert M. Huisman, Vijay S. Iyengar
Symbolic implication in test generation. EURO-DAC (1991)
Leendert M. Huisman, Raja Daoud
Fault simulation of logic designs on parallel processors with distributed memory. ITC (1990)
Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
SLS-a fast switch-level simulator [for MOS]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (8) (1988)
Larry Carter, Leendert M. Huisman, Tom W. Williams
TRIM: testability range by ignoring the memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7 (1) (1988)
Leendert M. Huisman
The reliability of approximate testability measures. IEEE Des. Test 5 (6) (1988)
Leendert M. Huisman, Larry Carter, Tom W. Williams
TRIM : Testability Range by Ignoring the Memory. ITC (1986)
Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Vijay S. Iyengar, Gabriel M. Silberman
SLS - a fast switch level simulator for verification and fault coverage analysis. DAC (1986)
Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo
Fast Pass-Transistor Simulation for Custom MOS Circuits. IEEE Des. Test 1 (1) (1984)
Zeev Barzilai, Daniel K. Beece, Leendert M. Huisman, Gabriel M. Silberman
Using a Hardware Simulation Engine for Custom MOS Structured Designs. IBM J. Res. Dev. 28 (5) (1984)
Zeev Barzilai, Leendert M. Huisman, Gabriel M. Silberman, Donald T. Tang, Lin S. Woo
Simulating pass transistor circuits using logic simulation machines. DAC (1983)