Jim Plusquellic

Publication Activity (10 Years)

Years Active: 2001-2024
Publications (10 Years): 46

Top Topics

Information Leakage

Top Venues

Publications

Idris Somoye, Jim Plusquellic, Tom J. Mannos, Brian Dziki
An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor. Cryptogr. 8 (2) (2024)
Idris Somoye, Tom J. Mannos, Brian Dziki, Jim Plusquellic
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43 (6) (2024)
Jenilee Jao, I. Wilcox, Sriram Thotakura, Calvin Chan, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev
An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions. J. Hardw. Syst. Secur. 7 (4) (2023)
Md. Sadman Siraj, Aisha B. Rahman, Eirini-Eleni Tsiropoulou, Symeon Papavassiliou, Jim Plusquellic
Symbiotic Positioning, Navigation, and Timing. DCOSS-IoT (2023)
Md. Sadman Siraj, Eirini-Eleni Tsiropoulou, Symeon Papavassiliou, Jim Plusquellic
SAFE: Secure Symbiotic Positioning, Navigation, and Timing. GLOBECOM (2023)
Jenilee Jao, Ian Wilcox, Sriram Thotakura, Calvin Chan, Jim Plusquellic, Biliana S. Paskaleva, Pavel B. Bochev
Correction to: An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions. J. Hardw. Syst. Secur. 7 (4) (2023)
Jim Plusquellic, Eirini-Eleni Tsiropoulou, Cyrus Minwalla
Privacy-Preserving Authentication Protocols for IoT Devices Using the SiRF PUF. IEEE Trans. Emerg. Top. Comput. 11 (4) (2023)
Md Sadman Siraj, Aisha B. Rahman, Maria Diamanti, Eirini-Eleni Tsiropoulou, Symeon Papavassiliou, Jim Plusquellic
Orchestration of Reconfigurable Intelligent Surfaces for Positioning, Navigation, and Timing. MILCOM (2022)
Jim Plusquellic, Donald E. Owen, Tom J. Mannos, Brian Dziki
Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (3) (2022)
Fisayo Sangoleye, Md Sahabul Hossain, Eirini-Eleni Tsiropoulou, Jim Plusquellic
Network Economics-based Crowdsourcing in UAV-assisted Smart Cities Environments. DCOSS (2022)
Jim Plusquellic
Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA. Cryptogr. 6 (4) (2022)
Nafis Irtija, Jim Plusquellic, Eirini-Eleni Tsiropoulou, Joshua Goldberg, Daniel Lobser, Daniel Stick
Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing. CoRR (2022)
Saraju P. Mohanty, Jim Plusquellic, Garrett S. Rose, Wei Zhang, Maria K. Michael
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things. ACM J. Emerg. Technol. Comput. Syst. 18 (1) (2022)
Georgios Fragkos, Cyrus Minwalla, Jim Plusquellic, Eirini-Eleni Tsiropoulou
Local Trust in Internet of Things Based on Contract Theory. Sensors 22 (6) (2022)
Georgios Fragkos, Cyrus Minwalla, Eirini-Eleni Tsiropoulou, Jim Plusquellic
Enhancing Privacy in PUF-Cash through Multiple Trusted Third Parties and Reinforcement Learning. ACM J. Emerg. Technol. Comput. Syst. 18 (1) (2022)
Md Sahabul Hossain, Nafis Irtija, Eirini-Eleni Tsiropoulou, Jim Plusquellic, Symeon Papavassiliou
Reconfigurable Intelligent Surfaces enabling Positioning, Navigation, and Timing Services. ICC (2022)
Nafis Irtija, Eirini-Eleni Tsiropoulou, Cyrus Minwalla, Jim Plusquellic
True Random Number Generation with the Shift-register Reconvergent-Fanout (SiRF) PUF. HOST (2022)
Donald E. Owen, Jithin Joseph, Jim Plusquellic, Tom J. Mannos, Brian Dziki
Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor. Cryptogr. 6 (3) (2022)
Derek Heeger, Maeve Garigan, Eirini-Eleni Tsiropoulou, Jim Plusquellic
Secure LoRa Firmware Update with Adaptive Data Rate Techniques. Sensors 21 (7) (2021)
Georgios Fragkos, Cyrus Minwalla, Jim Plusquellic, Eirini-Eleni Tsiropoulou
Artificially Intelligent Electronic Money. IEEE Consumer Electron. Mag. 10 (4) (2021)
Kelly Rael, Georgios Fragkos, Jim Plusquellic, Eirini-Eleni Tsiropoulou
UAV-enabled Human Internet of Things. DCOSS (2020)
Derek Heeger, Maeve Garigan, Eirini-Eleni Tsiropoulou, Jim Plusquellic
Secure Energy Constrained LoRa Mesh Network. ADHOC-NOW (2020)
Derek Heeger, Maeve Garigan, Jim Plusquellic
Adaptive Data Rate Techniques for Energy Constrained Ad Hoc LoRa Networks. GIoTS (2020)
Ivan Bow, Nahome Bete, Fareena Saqib, Wenjie Che, Chintan Patel, Ryan W. Robucci, Calvin Chan, Jim Plusquellic
Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity. Cryptogr. 4 (2) (2020)
Mitchell T. Martin, Jim Plusquellic
NotchPUF: Printed Circuit Board PUF Based on Microstrip Notch Filter. Cryptogr. 4 (2) (2020)
Georgios Fragkos, Cyrus Minwalla, Jim Plusquellic, Eirini-Eleni Tsiropoulou
Reinforcement Learning Toward Decision-Making for Multiple Trusted-Third-Parties in PUF-Cash. WF-IoT (2020)
Derek Heeger, Jim Plusquellic
Analysis of IoT Authentication Over LoRa. DCOSS (2020)
Jeff Calhoun, Cyrus Minwalla, Charles Helmich, Fareena Saqib, Wenjie Che, Jim Plusquellic
Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash). Cryptogr. 3 (3) (2019)
Ali Shuja Siddiqui, Geraldine Shirley, Shreya Bendre, Girija Bhagwat, Jim Plusquellic, Fareena Saqib
Secure Design Flow of FPGA Based RISC-V Implementation. IVSW (2019)
Domenic Forte, Swarup Bhunia, Ramesh Karri, Jim Plusquellic, Mark M. Tehranipoor
IEEE International Symposium on Hardware Oriented Security and Trust (HOST): Past, Present, and Future. ITC (2019)
Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib
Multilayer Camouflaged Secure Boot for SoCs. MTV (2019)
Wenjie Che, Fareena Saqib, Jim Plusquellic
Novel Offset Techniques for Improving Bitstring Quality of a Hardware-Embedded Delay PUF. IEEE Trans. Very Large Scale Integr. Syst. 26 (4) (2018)
Jim Plusquellic, Matthew Areno
Correlation-Based Robust Authentication (Cobra) Using Helper Data Only. Cryptogr. 2 (3) (2018)
Wenjie Che, Manel Martínez-Ramón, Fareena Saqib, Jim Plusquellic
Delay model and machine learning exploration of a hardware-embedded delay PUF. HOST (2018)
Ali Shuja Siddiqui, Yutian Gui, David Lawrence, Stuart Laval, Jim Plusquellic, Madhav Manjrekar, Badrul H. Chowdhury, Fareena Saqib
Hardware Assisted Security Architecture for Smart Grid. IECON (2018)
Don Owen Jr., Derek Heeger, Calvin Chan, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic
An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays. Cryptogr. 2 (3) (2018)
Goutham Pocklassery, Wenjie Che, Fareena Saqib, Matthew Areno, Jim Plusquellic
Self-authenticating secure boot for FPGAs. HOST (2018)
Wenjie Che, Venkata K. Kajuluri, Mitchell T. Martin, Fareena Saqib, Jim Plusquellic
Analysis of Entropy in a Hardware-Embedded Delay PUF. Cryptogr. 1 (1) (2017)
Wenjie Che, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic
Leveraging Distributions in Physical Unclonable Functions. Cryptogr. 1 (3) (2017)
Wenjie Che, Mitchell T. Martin, Goutham Pocklassery, Venkata K. Kajuluri, Fareena Saqib, Jim Plusquellic
A Privacy-Preserving, Mutual PUF-Based Authentication Protocol. Cryptogr. 1 (1) (2017)
Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib
Secure communication over CANBus. MWSCAS (2017)
Wenjie Che, Jim Plusquellic, Fareena Saqib
A novel offset method for improving bitstring quality of a Hardware-Embedded delay PUF. HOST (2017)
Ali Shuja Siddiqui, Chia-Che Lee, Wenjie Che, Jim Plusquellic, Fareena Saqib
Secure intra-vehicular communication over CANFD. AsianHOST (2017)
Fengchao Zhang, Shuo Yang, Jim Plusquellic, Swarup Bhunia
Current based PUF exploiting random variations in SRAM cells. DATE (2016)
Dylan Ismari, Jim Plusquellic, Charles Lamech, Swarup Bhunia, Fareena Saqib
On detecting delay anomalies introduced by hardware trojans. ICCAD (2016)
Ali Shuja Siddiqui, Yutian Gui, Jim Plusquellic, Fareena Saqib
Poster: Hardware based security enhanced framework for automotives. VNC (2016)
Fareena Saqib, Aindrik Dutta, Jim Plusquellic, Philip Ortiz, Marios S. Pattichis
Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF). IEEE Trans. Computers 64 (1) (2015)
Fareena Saqib, Dylan Ismari, Charles Lamech, Jim Plusquellic
Within-Die Delay Variation Measurement and Power Transient Analysis Using REBEL. IEEE Trans. Very Large Scale Integr. Syst. 23 (4) (2015)
Charalambos Konstantinou, Michail Maniatakos, Fareena Saqib, Shiyan Hu, Jim Plusquellic, Yier Jin
Cyber-physical systems: A security perspective. ETS (2015)
Wenjie Che, Fareena Saqib, Jim Plusquellic
PUF-Based Authentication. ICCAD (2015)
Dylan Ismari, Jim Plusquellic
IP-level implementation of a resistance-based physical unclonable function. HOST (2014)
Wenjie Che, Jim Plusquellic, Swarup Bhunia
A non-volatile memory based physically unclonable function without helper data. ICCAD (2014)
Swarup Bhunia, Miron Abramovici, Dakshi Agrawal, Paul Bradley, Michael S. Hsiao, Jim Plusquellic, Mohammad Tehranipoor
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. IEEE Des. Test 30 (3) (2013)
Jim Aarestad, Philip Ortiz, Dhruva Acharyya, Jim Plusquellic
HELP: A Hardware-Embedded Delay PUF. IEEE Des. Test 30 (2) (2013)
J. Ju, Ray Chakraborty, Charles Lamech, Jim Plusquellic
Stability analysis of a physical unclonable function based on metal resistance variations. HOST (2013)
Jim Aarestad, Jim Plusquellic, Dhruva Acharyya
Error-tolerant bit generation techniques for use with a hardware-embedded path delay PUF. HOST (2013)
Raj Chakraborty, Charles Lamech, Dhruva Acharyya, Jim Plusquellic
A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique. DAC (2013)
Jing Ju, Jim Plusquellic, Raj Chakraborty, Reza M. Rad
Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors. HOST (2012)
Charles Lamech, Jim Plusquellic
Trojan detection based on delay variations measured using a high-precision, low-overhead embedded test structure. HOST (2012)
Matthew Areno, Jim Plusquellic
Securing Trusted Execution Environments with PUF Generated Secret Keys. TrustCom (2012)
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic
A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. IEEE Trans. Very Large Scale Integr. Syst. 20 (1) (2012)
Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal
Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC (2011)
Charles Lamech, Reza M. Rad, Mohammad Tehranipoor, Jim Plusquellic
An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities. IEEE Trans. Inf. Forensics Secur. 6 (3-2) (2011)
Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal
Measuring within-die spatial variation profile through power supply current measurements. ISQED (2011)
Charles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal
REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. ICCAD (2011)
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. DAC (2010)
Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic
s. IEEE Trans. Inf. Forensics Secur. 5 (4) (2010)
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic
A layout-aware approach for improving localized switching to detect hardware Trojans in integrated circuits. WIFS (2010)
Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic
Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC (2010)
Ryan Helinski, Dhruva Acharyya, Jim Plusquellic
A physical unclonable function defined using power distribution system equivalent resistance variations. DAC (2009)
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquellic
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time. HOST (2009)
Reza M. Rad, Jim Plusquellic
A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals. J. Electron. Test. 25 (2-3) (2009)
Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic
Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD (2009)
Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic
Detecting Malicious Inclusions in Secure Hardware: Challenges and Solutions. HOST (2008)
Reza M. Rad, Jim Plusquellic, Mohammad Tehranipoor
Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals. HOST (2008)
Reza M. Rad, Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic
Power supply signal calibration techniques for improving detection resolution to hardware Trojans. ICCAD (2008)
Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic
Securing Designs against Scan-Based Side-Channel Attacks. IEEE Trans. Dependable Secur. Comput. 4 (4) (2007)
Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. IEEE Des. Test Comput. 23 (4) (2006)
Abhishek Singh, Jim Plusquellic, Dhananjay S. Phatak, Chintan Patel
Testing. J. Electron. Test. 22 (3) (2006)
Jeremy Lee, Mohammad Tehranipoor, Jim Plusquellic
A Low-Cost Solution for Protecting IPs Against Scan-Based Side-Channel Attacks. VTS (2006)
Dhruva Acharyya, Jim Plusquellic
Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. VTS (2005)
Chintan Patel, Abhishek Singh, Jim Plusquellic
Defect Detection Using Quiescent Signal Analysis. J. Electron. Test. 21 (5) (2005)
Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic
At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS (2005)
Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic
Securing Scan Design Using Lock and Key Technique. DFT (2005)
Abhishek Singh, Chintan Patel, Jim Plusquellic
On-Chip Impulse Response Generation for Analog and Mixed-Signal Testing. ITC (2004)
Abhishek Singh, Chintan Patel, Jim Plusquellic
Fault Simulation Model for i{DDT} Testing: An Investigation. VTS (2004)
Chintan Patel, Abhishek Singh, Jim Plusquellic
Defect detection under Realistic Leakage Models using Multiple IDDQ Measurement. ITC (2004)
Sanat Kamal Bahl, Jim Plusquellic
FPGA implementation of a fast Hadamard transformer for WCDMA. FPGA (2003)
Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. J. Electron. Test. 19 (6) (2003)
Abhishek Singh, Jitin Tharian, Jim Plusquellic
Path Delay Estimation using Power Supply Transient Signals: A Comparative Study using Fourier and Wavelet Analysis. ICCAD (2003)
Dhananjay S. Phatak, Tom Goff, Jim Plusquellic
IP-in-IP tunneling to enable the simultaneous use of multiple IP interfaces for network level connection striping. Comput. Networks 43 (6) (2003)
Dhruva Acharyya, Jim Plusquellic
Impedance Profile of a Commercial Power Grid and Test System. ITC (2003)
Abhishek Singh, Jim Plusquellic, Anne E. Gattiker
Power Supply Transient Signal Analysis Under Real Process and Test Hardware Models. VTS (2002)
Chintan Patel, Jim Plusquellic
A Process and Technology-Tolerant IDDQ Method for IC Diagnosis. VTS (2001)
Jim Plusquellic
IC Diagnosis Using Multiple Supply Pad IDDQs. IEEE Des. Test Comput. 18 (1) (2001)