Jacob Savir

Publication Activity (10 Years)

Years Active: 1980-2006
Publications (10 Years): 0

Publications

Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
BIST Pretest of ICs: Risks and Benefits. VTS (2006)
Zhen Guo, Jacob Savir
Coefficient-based test of parametric faults in analog circuits. IEEE Trans. Instrum. Meas. 55 (1) (2006)
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
Effect of BIST Pretest on IC Defect Level. IEICE Trans. Inf. Syst. (10) (2006)
Jacob Savir
Built-in online and offline test of airborne digital systems. IEEE Trans. Instrum. Meas. 54 (3) (2005)
Yoshiyuki Nakamura, Jacob Savir, Hideo Fujiwara
Defect Level vs. Yield and Fault Coverage in the Presence of an Unreliable BIST. IEICE Trans. Inf. Syst. (6) (2005)
Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths. IEICE Trans. Inf. Syst. (8) (2005)
Zhen Guo, Jacob Savir
Analog Circuit Test Using Transfer Function Coefficient Estimates. IEICE Trans. Inf. Syst. (3) (2004)
Amit M. Sheth, Jacob Savir
Scan Latch Design for Test Applications. J. Electron. Test. 20 (2) (2004)
Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara
Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. Asian Test Symposium (2004)
Zhen Guo, Jacob Savir
Analog Circuit Test using Transfer Function Coe .cient Estimates. ITC (2003)
Jacob Savir, Zhen Guo
Test limitations of parametric faults in analog circuits. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Amit M. Sheth, Jacob Savir
Single-clock, single-latch, scan design. IEEE Trans. Instrum. Meas. 52 (5) (2003)
Jacob Savir, Zhen Guo
On the Detectability of Parametric Faults in Analog Circuits. ICCD (2002)
Jacob Savir, Zhen Guo
Test Limitations of Parametric Faults in Analog Circuits. Asian Test Symposium (2002)
Zhen Guo, Jacob Savir
Observer-Based Test of Analog Linear Time-Invariant Circuits. DELTA (2002)
Jacob Savir
Test Generators Need to be Modified to Handle CMOS Designs. VLSI Design 2001 (4) (2001)
Jacob Savir
BIST Analysis of an Embedded Memory Associated Logic. VLSI Design 2001 (4) (2001)
Zhen Guo, Xi Min Zhang, Jacob Savir, Yun-Qing Shi
On Test and Characterization of Analog Linear Time-Invariant Circuits Using Neural Networks. Asian Test Symposium (2001)
Jacob Savir
BIST-Based Fault Diagnosis in the Presence of Embedded Memories. VLSI Design 2001 (4) (2001)
Jacob Savir
On testing safety-sensitive digital systems. Asian Test Symposium (2000)
Qiang Peng, Miron Abramovici, Jacob Savir
MUST: multiple-stem analysis for identifying sequentially untestable faults. ITC (2000)
Jacob Savir
Distributed BIST Architecture to Combat Delay Faults. J. Electron. Test. 16 (4) (2000)
Jacob Savir
On-line and off-line test of airborne digital systems: a reliability study. ITC (2000)
Jacob Savir
Distributed Generation of Weighted Random Patterns. IEEE Trans. Computers 48 (12) (1999)
Jacob Savir
Design for Testability to Combat Delay Faults. ICCD (1999)
Jacob Savir
Random Pattern Testability of Control and Address Circuitry of an Embedded Memory with Feed-Forward Data-Path Connections. J. Electron. Test. 15 (3) (1999)
Jacob Savir
Memory Chip BIST Architecture. Great Lakes Symposium on VLSI (1999)
Jacob Savir
BIST Diagnostics, Part 1: Simulation Models. Asian Test Symposium (1998)
Jacob Savir
Distributed Generation of Weighted Random Patterns. VTS (1998)
Jacob Savir
On-Chip Weighted Random Patterns. J. Electron. Test. 13 (1) (1998)
Jacob Savir
Redundancy revisited. IEEE Trans. Very Large Scale Integr. Syst. 6 (4) (1998)
Jacob Savir
Random Pattern Testability of Memory Control Logic. IEEE Trans. Computers 47 (3) (1998)
Jacob Savir
Salvaging Test Windows in BIST Diagnostics. IEEE Trans. Computers 47 (4) (1998)
Jacob Savir
Random pattern testability of memory address logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17 (12) (1998)
Jacob Savir
Scan Latch Design for Delay Test. ITC (1997)
Jacob Savir
BIST-Based Fault Diagnosis in the Presence of Embedded Memories. ICCD (1997)
Jacob Savir
Module Level Weighted Random Patterns. J. Electron. Test. 10 (3) (1997)
Jacob Savir
On The Tradeoff Between Number of Clocks and Number of Latches in Shift Registers. Asian Test Symposium (1997)
Jacob Savir
On Chip Weighted Random Patterns. Asian Test Symposium (1997)
Jacob Savir
Salvaging test windows in BIST diagnostic. VTS (1997)
Jacob Savir
Delay Test Generation: A Hardware Perspective. J. Electron. Test. 10 (3) (1997)
Jacob Savir
Reduced Latch Count Shift Registers. J. Electron. Test. 11 (2) (1997)
Jacob Savir
Random pattern testability of memory control logic. VTS (1997)
Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
Delay Fault Testing: How Robust are Our Models? VTS (1996)
Jacob Savir
Reducing the MISR Size. IEEE Trans. Computers 45 (8) (1996)
Jacob Savir
On shrinking wide compressors. VTS (1995)
Jacob Savir
Module level weighted random patterns. Asian Test Symposium (1995)
Jacob Savir
Shrinking wide compressors [BIST]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14 (11) (1995)
Jacob Savir
Generator choices for delay test. Asian Test Symposium (1995)
Jacob Savir, Srinivas Patil
Broad-side delay test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13 (8) (1994)
Jacob Savir, Srinivas Patil
On broad-side delay test. VTS (1994)
Jacob Savir, Srinivas Patil
On broad-side delay test. IEEE Trans. Very Large Scale Integr. Syst. 2 (3) (1994)
Jacob Savir, Srinivas Patil
Scan-based transition test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12 (8) (1993)
Jacob Savir, Paul H. Bardell
Built-In Self-Test: Milestones and Challenges. VLSI Design 1 (1) (1993)
A. Boneh, Jacob Savir
Statistical Resistance to Detection. IEEE Trans. Computers 41 (1) (1992)
Jacob Savir
Skewed-Load Transition Test: Part 1, Calculus. ITC (1992)
Jacob Savir, William H. McAnney
A Multiple Seed Linear Feedback Shift Register. IEEE Trans. Computers 41 (2) (1992)
Jacob Savir, Robert F. Berry
AC strength of a pattern generator. J. Electron. Test. 3 (2) (1992)
Jacob Savir
Developments in delay testing. VTS (1992)
Srinivas Patil, Jacob Savir
Skewed-Load Transition Test: Part 2, Coverage. ITC (1992)
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
Testing for Coupled Cells in Random-Access Memories. IEEE Trans. Computers 40 (10) (1991)
Jacob Savir, Paul H. Bardell
Partitioning of polynomial tasks: test generation, an example. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10 (11) (1991)
Jacob Savir, Robert F. Berry
At-Speed Test is not Necessarily an AC Test. ITC (1991)
Jacob Savir
AC product defect level and yield loss. ITC (1990)
Jacob Savir, William H. McAnney
A multiple seed linear feedback shift register. ITC (1990)
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
Testing for Coupled Cells in Random-Access Memories. ITC (1989)
Jacob Savir
Why Partial Design Verification Works Better Than It Should. DAC (1988)
William H. McAnney, Jacob Savir
Built-In Checking of the Correct Self-Test Signature. IEEE Trans. Computers 37 (9) (1988)
Jacob Savir, William H. McAnney
Identification of Failing Tests with Cycling Registers. ITC (1988)
Jacob Savir, William H. McAnney
Random Pattern Testability of Delay Faults. IEEE Trans. Computers 37 (3) (1988)
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
Fault Propagation Through Embedded Multiport Memories. IEEE Trans. Computers 36 (5) (1987)
Jacob Savir
The Bidirectional Double Latch (BDDL). IEEE Trans. Computers 35 (1) (1986)
William H. McAnney, Jacob Savir
Built-In Checking of the Correct Self-Test Signature. ITC (1986)
Jacob Savir, William H. McAnney
Random Pattern Testability of Delay Faults. ITC (1986)
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
Random Pattern Testing for Data-Line Faults in an Embedded Multiport Memory. ITC (1985)
Jacob Savir, William H. McAnney, Salvatore R. Vecchio
Random Pattern Testing for Address-Line Faults in an Embedded Multiport Memory. ITC (1985)
Thomas H. Spencer, Jacob Savir
Layout Influences Testability. IEEE Trans. Computers 34 (3) (1985)
Jacob Savir, Paul H. Bardell
On Random Pattern Test Length. IEEE Trans. Computers 33 (6) (1984)
Jacob Savir, Gary S. Ditlow, Paul H. Bardell
Random Pattern Testability. IEEE Trans. Computers 33 (1) (1984)
Jacob Savir
A New Empirical Test for the Quality of Random Integer Generators. IEEE Trans. Computers 32 (10) (1983)
Jacob Savir, Paul H. Bardell
On Random Pattern Test Length. ITC (1983)
Jacob Savir
Good Controllability and Observability Do Not Guarantee Good Testability. IEEE Trans. Computers 32 (12) (1983)
Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith
The Weighted Syndrome Sums Approach to VLSI Testing. IEEE Trans. Computers 30 (12) (1981)
Zeev Barzilai, Jacob Savir, George Markowsky, Merlin G. Smith
VLSI Self-Testing Based on Syndrome Techniques. ITC (1981)
Jacob Savir
Syndrome-Testing of "Syndrome-Untestable" Combinational Circuits. IEEE Trans. Computers 30 (8) (1981)
Jacob Savir
Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection. IEEE Trans. Computers 29 (5) (1980)
Jacob Savir
Syndrome-Testable Design of Combinational Circuits. IEEE Trans. Computers 29 (6) (1980)
Jacob Savir
Detection of Single Intermittent Faults in Sequential Circuits. IEEE Trans. Computers 29 (7) (1980)