Gary S. Ditlow

Publication Activity (10 Years)

Years Active: 1984-2011
Publications (10 Years): 0

Publications

Gary S. Ditlow, Robert K. Montoye, Salvatore N. Storino, Sherman M. Dance, Sebastian Ehrenreich, Bruce M. Fleischer, Thomas W. Fox, Kyle M. Holmes, Junichi Mihara, Yutaka Nakamura, Shohji Onishi, Robert Shearer, Dieter F. Wendel, Leland Chang
A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. ISSCC (2011)
Matthew M. Ziegler, Gary S. Ditlow, Stephen V. Kosonocky, Zhenyu Qi, Mircea R. Stan
Structured and tuned array generation (STAG) for high-performance random logic. ACM Great Lakes Symposium on VLSI (2007)
David Moran, Gary S. Ditlow, Daria Dooling, Ralph Williams, Tom Wilkins
Integrated Manufacturing and Development (IMaD). SC (1999)
Gary S. Ditlow, Anshul Gupta, Richard L. Moore, David Moran, Ralph Williams, Tom Wilkins
Parallel Analysis of IC Power Distribution Networks. PPSC (1999)
David A. Zein, Oliver P. Engel, Gary S. Ditlow
Algorithms for the design verification of bipolar array chips. VTS (1992)
David A. Zein, Oliver P. Engel, Gary S. Ditlow
HLSIM-a new hierarchical logic simulator in APL. VTS (1992)
David A. Zein, Oliver P. Engel, Gary S. Ditlow
HLSIM - A New Hierarchical Logic Simulator and Netlist Converter. DAC (1992)
Jacob Savir, Gary S. Ditlow, Paul H. Bardell
Random Pattern Testability. IEEE Trans. Computers 33 (1) (1984)