Prab Varma

Publication Activity (10 Years)

Years Active: 1984-2016
Publications (10 Years): 1

Top Topics

Future Directions

Web Intelligence

Top Venues

Asian Test Symposium

Publications

Prab Varma, Miroslav N. Velev
Welcome Message. HLDVT (2016)
Prab Varma
Current and Future Directions in Automatic Test Pattern Generation for Power Delivery Network Validation. Asian Test Symposium (2012)
Prab Varma
Verification evolution or industrial revolution? IEEE Des. Test Comput. 21 (2) (2004)
Prab Varma
Design Verification Problems: Test To The Rescue? ITC (2003)
Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma
ATPG for Design Errors-Is It Possible? VTS (2001)
Bechir Ayari, Prab Varma
Test Cycle Count Reduction in a Parallel Scan BIST Environment. J. Electron. Test. 16 (5) (2000)
Prab Varma
System chip test: are we there yet? ITC (1998)
Bechir Ayari, Prab Varma
Test Cycle Count Reduction in a Parallel Scan BIST Environment. Asian Test Symposium (1998)
Prab Varma, Sandeep Bhatia
A structured test re-use methodology for core-based system chips. ITC (1998)
Prab Varma
System Chip Test Challenges, Are There Solutions Today? (Panel). DAC (1998)
Sandeep Bhatia, Prab Varma
Test Compaction in a Parallel Access Scan Environment. Asian Test Symposium (1997)
Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma
Delay Fault Testing: How Robust are Our Models? VTS (1996)
Sandeep Bhatia, Tushar Gheewala, Prab Varma
A Unifying Methodology for Intellectual Property and Custom Logic Testing. ITC (1996)
Prab Varma
Optimizing Product Profitability - The Test Way. ITC (1995)
Prab Varma
On Path-Delay Testing in a Standard Scan Environment. ITC (1994)
Prab Varma, Tushar Gheewala
The economics of scan-path design for testability. J. Electron. Test. 5 (2-3) (1994)
Prab Varma, Tushar Gheewala
Delay Testing Using a Matrix of Accessible Storage. ITC (1993)
Prab Varma
Scan DFT: Why More Can Cost Less. ITC (1993)
Prab Varma
On test generation for path delay faults in ASICs. VTS (1992)
Prab Varma
TDRC-a symbolic simulation based design for testability rules checker. ITC (1990)
S. B. Tan, K. Totton, Keith Baker, Prab Varma, R. Porter
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits. DAC (1987)
Prab Varma, Anthony P. Ambler, Keith Baker
An Analysis of the Economics of Self Test. ITC (1984)