Low Cost Concurrent Error Detection Strategy for the Control Logic of High Performance Microprocessors and Its Application to the Instruction Decoder.
Daniele RossiMartin OmañaG. GarrammoneCecilia MetraAbhijit JasRajesh GalivanchePublished in: J. Electron. Test. (2013)
Keyphrases
- error detection
- low cost
- fault isolation
- error recovery
- error correction
- error control
- error resilient
- error correcting
- fault tolerance
- data cleansing
- data acquisition
- single chip
- control system
- real time
- instruction set
- neural network
- low power consumption
- computer architecture
- low power
- low complexity
- response time
- personal computer
- fault tolerant
- complex systems