DFT Timing Design Methodology for Logic BIST.
Yasuo SatoMotoyuki SatoKoki TsutsumidaKazumi HatayamaKazuyuki NomotoPublished in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2003)
Keyphrases
- design methodology
- asynchronous circuits
- built in self test
- chip design
- design criteria
- design process
- physical design
- design methodologies
- fuzzy neural network
- design procedure
- discrete fourier transform
- object oriented
- hw sw
- real world
- artificial neural networks
- network structure
- integrated circuit
- web services
- knowledge base