Xijiang Lin

Publication Activity (10 Years)

Years Active: 1998-2021
Publications (10 Years): 14

Top Topics

Fluorescence Microscopy Images

Generation Algorithm

Fault Detection

Generating High Quality

Top Venues

Publications

Wei Li, Shih-Yu Yang, Khen Wee, Ricardo Sanchez, Jay Desai, Kun-Han Tsai, Xijiang Lin
Timing Critical Path Validation for Intel ATOM Cores Using Structural Test. VTS (2021)
Xijiang Lin, Wu-Tung Cheng, Takeo Kobayashi, Andreas Glowatz
On Modeling CMOS Library Cells for Cell Internal Fault Test Pattern Generation. ATS (2021)
Irith Pomeranz, Xijiang Lin
Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 29 (2) (2021)
Uri Shpiro, Khen Wee, Kun-Han Tsai, Justyna Zawada, Xijiang Lin
Test Challenges of Intel IA Cores. ITC (2020)
Naixing Wang, Chen Wang, Kun-Han Tsai, Wu-Tung Cheng, Xijiang Lin, Mark Kassab, Irith Pomeranz
TEA: A Test Generation Algorithm for Designs with Timing Exceptions. ATS (2019)
Xijiang Lin, Sudhakar M. Reddy
On Generating Fault Diagnosis Patterns for Designs with X Sources. ETS (2019)
Naixing Wang, Bo Yao, Xijiang Lin, Irith Pomeranz
Functional Broadside Test Generation Using a Commercial ATPG Tool. ISVLSI (2017)
Xijiang Lin
On applying scan based structural test for designs with dual-edge triggered flip-flops. ITC (2017)
Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS (2016)
Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS (2016)
Dong Xiang, Kele Shen, Bhargab B. Bhattacharya, Xiaoqing Wen, Xijiang Lin
Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35 (3) (2016)
Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSI Design (2015)
Xijiang Lin, Sudhakar M. Reddy
On generating high quality tests based on cell functions. ITC (2015)
Xijiang Lin, Wu-Tung Cheng, Janusz Rajski
On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults. ATS (2015)
Xijiang Lin, Mark Kassab, Janusz Rajski
Using dynamic shift to reduce test data volume in high-compression designs. ETS (2014)
Dong Xiang, Jianbo Li, Krishnendu Chakrabarty, Xijiang Lin
Test compaction for small-delay defects using an effective path selection scheme. ACM Trans. Design Autom. Electr. Syst. 18 (3) (2013)
Kun-Han Tsai, Xijiang Lin
Multicycle-aware At-speed Test Methodology. Asian Test Symposium (2013)
Xijiang Lin, Janusz Rajski
On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium (2012)
Xijiang Lin
Power Supply Droop and Its Impacts on Structural At-Speed Testing. Asian Test Symposium (2012)
Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer
Power Aware Embedded Test. Asian Test Symposium (2011)
Xijiang Lin
Low power testing - What can commercial DFT tools provide? IGCC (2011)
Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab
Low capture power at-speed test in EDT environment. ITC (2010)
Dat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson
Detecting and diagnosing open defects. ITC (2010)
Tom Waayers, Richard Morren, Xijiang Lin, Mark Kassab
Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domains. ITC (2010)
Xijiang Lin, Janusz Rajski
Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium (2010)
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
On Reducing Scan Shift Activity at RTL. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (7) (2010)
Xijiang Lin, Mark Kassab
Test Generation for Designs with On-Chip Clock Generators. Asian Test Symposium (2009)
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28 (11) (2009)
Xijiang Lin, Janusz Rajski
Test Power Reduction by Blocking Scan Cell Outputs. ATS (2008)
Xijiang Lin, Yu Huang
Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. J. Electron. Test. 24 (4) (2008)
Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer
Low Power Scan Shift and Capture in the EDT Environment. ITC (2008)
Elif Alpaslan, Yu Huang, Xijiang Lin, Wu-Tung Cheng, Jennifer Dworak
Reducing Scan Shift Power at RTL. VTS (2008)
Xijiang Lin, Janusz Rajski
Test Generation for Interconnect Opens. ITC (2008)
Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality CoRR (2007)
Yu Huang, Xijiang Lin
Programmable Logic BIST for At-speed Test. ATS (2007)
Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
Low Shift and Capture Power Scan Tests. VLSI Design (2007)
Xijiang Lin, Mark Kassab, Janusz Rajski
Test Generation for Timing-Critical Transition Faults. ATS (2007)
Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. 24 (3) (2007)
Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC (2006)
Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS (2006)
Xijiang Lin, Janusz Rajski
The Impacts of Untestable Defects on Transition Fault Testing. VTS (2006)
Xijiang Lin, Kun-Han Tsai, Chen Wang, Mark Kassab, Janusz Rajski, Takeo Kobayashi, Randy Klingenberg, Yasuo Sato, Shuji Hamada, Takashi Aikyo
Timing-Aware ATPG for High Quality At-speed Testing of Small Delay Defects. ATS (2006)
Matthias Beck, Olivier Barondeau, Frank Poehl, Xijiang Lin, Ron Press
Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study. VTS (2005)
Xijiang Lin, Janusz Rajski
Propagation delay fault: a new fault model to test delay faults. ASP-DAC (2005)
Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Xijiang Lin, Ron Press
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality. DATE (2005)
Xijiang Lin, Rob Thompson
Test generation for designs with multiple clocks. DAC (2003)
Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
High-Frequency, At-Speed Scan Testing. IEEE Des. Test Comput. 20 (5) (2003)
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski
Conflict driven techniques for improving deterministic test pattern generation. ICCAD (2002)
Nandu Tendolkar, Rajesh Raina, Rick Woltenberg, Xijiang Lin, Bruce Swanson, Greg Aldrich
Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture. VTS (2002)
Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium (2001)
Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy
On static test compaction and test pattern ordering for scan designs. ITC (2001)
Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS (2000)
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
Techniques for improving the efficiency of sequential circuit test generation. ICCAD (1999)
Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS (1999)
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
Full Scan Fault Coverage With Partial Scan. DATE (1999)
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
On finding undetectable and redundant faults in synchronous sequential circuits. ICCD (1998)
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design (1998)
Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy
On Removing Redundant Faults in Synchronous Sequential Circuits. VTS (1998)