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Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
Matthias Beck
Olivier Barondeau
Martin Kaibel
Frank Poehl
Xijiang Lin
Ron Press
Published in:
CoRR (2007)
Keyphrases
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implementation details
built in self test
high speed
statistical tests
experimental design
micron cmos
case study
high quality
test data
chip design