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Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
Matthias Beck
Olivier Barondeau
Martin Kaibel
Frank Poehl
Xijiang Lin
Ron Press
Published in:
DATE (2005)
Keyphrases
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implementation details
built in self test
high speed
test cases
high quality
circuit design
statistical significance
micron cmos
chip design
design process
low cost
user interface
experimental design
single chip
cost effectiveness
power dissipation
vlsi implementation
case study
neural network