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Low-Power Scan Operation in Test Compression Environment.
Dariusz Czysz
Mark Kassab
Xijiang Lin
Grzegorz Mrugalski
Janusz Rajski
Jerzy Tyszer
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2009)
Keyphrases
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low power
power consumption
high speed
low cost
wireless transmission
single chip
logic circuits
digital signal processing
real time
high power
low power consumption
vlsi circuits
compression ratio
vlsi architecture
power reduction
image compression
delay insensitive
gate array