Michinobu Nakao

Publication Activity (10 Years)

Years Active: 1995-2013
Publications (10 Years): 0

Top Topics

Wavelet Transform

Recognition Scheme

Top Venues

IEICE Trans. Electron.

Publications

Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko
Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. IEICE Trans. Electron. (1) (2013)
Masayuki Arai, Tatsuro Endo, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
Reduction of Area per Good Die for SoC Memory Built-In Self-Test. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Masayuki Arai, Kazuhiko Iwasaki, Michinobu Nakao, Iwao Suzuki
Hardware Overhead Reduction for Memory BIST. ITC (2008)
Wu-Tung Cheng, Brady Benware, Ruifeng Guo, Kun-Han Tsai, Takeo Kobayashi, Kazuyuki Maruo, Michinobu Nakao, Yoshiaki Fukui, Hideyuki Otake
Enhancing Transition Fault Model for Delay Defect Diagnosis. ATS (2008)
Kazumi Hatayama, Michinobu Nakao, Yoshikazu Kiyoshige, Koichiro Natsume, Yasuo Sato, Takaharu Nagumo
Application of High-Quality Built-In Test to Industrial Designs. ITC (2002)
Kazumi Hatayama, Michinobu Nakao, Yasuo Sato
At-Speed Built-in Test for Logic Circuits with Multiple Clocks. Asian Test Symposium (2002)
Michinobu Nakao, Yoshikazu Kiyoshige, Kazumi Hatayama, Yasuo Sato, Takaharu Nagumo
Test Generation for Multiple-Threshold Gate-Delay Fault Model. Asian Test Symposium (2001)
Yasuo Sato, Toyohito Ikeya, Michinobu Nakao, Takaharu Nagumo
A BIST approach for very deep sub-micron (VDSM) defects. ITC (2000)
Michinobu Nakao, Seiji Kobayashi, Kazumi Hatayama, Kazuhiko Iijima, Seiji Terada
Low overhead test point insertion for scan-based BIST. ITC (1999)
Michinobu Nakao, Kazumi Hatayama, Isao Higashi
Accelerated Test Points Selection Method for Scan-Based BIST. Asian Test Symposium (1997)
Hiroshi Date, Michinobu Nakao, Kazumi Hatayama
A parallel sequential test generation system DESCARTES based on real-valued logic simulation. Asian Test Symposium (1995)