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Reduction of Area per Good Die for SoC Memory Built-In Self-Test.

Masayuki AraiTatsuro EndoKazuhiko IwasakiMichinobu NakaoIwao Suzuki
Published in: IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2010)
Keyphrases
  • built in self test
  • memory usage
  • computing power
  • memory requirements
  • low power
  • low memory
  • database
  • integrated circuit
  • random access
  • memory footprint
  • decision making
  • low cost
  • memory space
  • reduction method
  • memory size