Shyue-Kung Lu

Publication Activity (10 Years)

Years Active: 1991-2023
Publications (10 Years): 31

Top Topics

Foreseeable Future

Defect Detection

Top Venues

J. Electron. Test.

Publications

Shyue-Kung Lu, Xin Dong
Integrated Progressive Built-In Self-Repair (IPBISR) Techniques for NAND Flash Memory. ITC-Asia (2023)
Shyue-Kung Lu, Zeng-Long Tsai
C Techniques for Protecting NAND Flash Memories. J. Electron. Test. 39 (4) (2023)
Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase
Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC-Asia (2022)
Shyue-Kung Lu, Zhi-Jia Liu, Masaki Hashizume
Fault Securing Techniques for Yield and Reliability Enhancement of RRAM. ATS (2022)
Shyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase
Fault Resilience Techniques for Flash Memory of DNN Accelerators. ITC (2022)
Taiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
Effective Switching Probability Calculation to Locate Hotspots in Logic Circuits. ITC-Asia (2022)
Shyue-Kung Lu, Shi-Chun Tseng, Kohei Miyase
Fine-Grained Built-In Self-Repair Techniques for NAND Flash Memories. ITC (2022)
Masao Ohmatsu, Yuto Ohtera, Yuki Ikiri, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Masaki Hashizume
Enhanced Interconnect Test Method for Resistive Open Defects in Final Tests with Relaxation Oscillators. ATS (2022)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase, Chun-Lung Hsu, Chi-Tien Sun
Fault-Aware Dependability Enhancement Techniques for Phase Change Memory. J. Electron. Test. 37 (4) (2021)
Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
ECC Caching Techniques for Protecting NAND Flash Memories. ITC-Asia (2020)
Shyue-Kung Lu, Zeng-Long Tsai, Chun-Lung Hsu, Chi-Tien Sun
Fault-Aware ECC Techniques for Reliability Enhancement of Flash Memory. VLSI-DAT (2020)
Shyue-Kung Lu, Shu-Chi Yu, Chun-Lung Hsu, Chi-Tien Sun, Masaki Hashizume, Hiroyuki Yotsuyanagi
Fault-Aware Dependability Enhancement Techniques for Flash Memories. IEEE Trans. Very Large Scale Integr. Syst. 28 (3) (2020)
Hanna Soneda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Electrical Field Test Method of Resistive Open Defects between Dies by Quiescent Currents through Embedded Diodes. 3DIC (2019)
Shyue-Kung Lu, Hung-Kai Huang, Chun-Lung Hsu, Chi-Tien Sun, Kohei Miyase
Retention-Aware Refresh Techniques for Reducing Power and Mitigation of Data Retention Faults in DRAM. J. Electron. Test. 35 (4) (2019)
Kohei Miyase, Yudai Kawano, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara
A Static Method for Analyzing Hotspot Distribution on the LSI. ITC-Asia (2019)
Christian M. Fuchs, Pai H. Chou, Xiaoqing Wen, Nadia M. Murillo, Gianluca Furano, Stefan Holst, Antonis Tavoularis, Shyue-Kung Lu, Aske Plaat, Kostas Marinis
A Fault-Tolerant MPSoC For CubeSats. DFT (2019)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase
Adaptive ECC Techniques for Reliability and Yield Enhancement of Phase Change Memory. IOLTS (2018)
Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume
Address Remapping Techniques for Enhancing Fabrication Yield of Embedded Memories. J. Electron. Test. 34 (4) (2018)
Shyue-Kung Lu, Hui-Ping Li, Kohei Miyase
Progressive ECC Techniques for Phase Change Memory. ATS (2018)
Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume
Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories. J. Electron. Test. 34 (5) (2018)
Fara Ashikin, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu, Zvi Roth
A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs. IEICE Trans. Inf. Syst. (8) (2018)
Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. DFT (2017)
Ayumu Kambara, Hiroyuki Yotsuyanagi, Daichi Miyoshi, Masaki Hashizume, Shyue-Kung Lu
Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs. ATS (2017)
Shyue-Kung Lu, Shu-Chi Yu, Masaki Hashizume, Hiroyuki Yotsuyanagi
Fault-Aware Page Address Remapping Techniques for Enhancing Yield and Reliability of Flash Memories. ATS (2017)
Shyue-Kung Lu, Hung-Kai Huang
Adaptive block-based refresh techniques for mitigation of data retention faults and reduction of refresh power. ITC-Asia (2017)
Kouhei Ohtani, Naho Osato, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
A defect level monitor of resistive open defect at interconnects in 3D ICs by injected charge volume. ISCIT (2017)
Yi-Wei Ma, Jiann-Liang Chen, Yao-Hong Tsai, Pen-Chan Chou, Shyue-Kung Lu, Sy-Yen Kuo
Integrated Heterogeneous Infrastructure for Indoor Positioning. SpaCCS Workshops (2016)
Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume
Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories. IEEE Trans. Very Large Scale Integr. Syst. 24 (8) (2016)
Widianto, Masaki Hashizume, Shohei Suenaga, Hiroyuki Yotsuyanagi, Akira Ono, Shyue-Kung Lu, Zvi Roth
A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs. IEICE Trans. Inf. Syst. (11) (2016)
Chih-Chieh Zheng, Shi-Yu Huang, Shyue-Kung Lu, Ting-Chi Wang, Kun-Han Tsai, Wu-Tung Cheng
Online slack-time binning for IO-registered die-to-die interconnects. ITC (2016)
Shyue-Kung Lu, Shang-Xiu Zhong, Masaki Hashizume
Adaptive ECC Techniques for Yield and Reliability Enhancement of Flash Memories. ATS (2016)
Shyue-Kung Lu, Shu-Ling Lin, Hao-Wei Lin, Masaki Hashizume
Hybrid scrambling technique for increasing the fabrication yield of NROM-Based ROMs. VLSI-DAT (2015)
Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen
Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. IEEE Trans. Computers 64 (5) (2015)
Kosuke Nanbara, Akihiro Odoriba, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Electrical interconnect test of 3D ICs made of dies without ESD protection circuits with a built-in test circuit. 3DIC (2015)
Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume
Integration of Hard Repair Techniques with ECC for Enhancing Fabrication Yield and Reliability of Embedded Memories. ATS (2015)
Shyue-Kung Lu, Hao-Wei Lin, Masaki Hashizume
An enhanced built-in self-repair technique for yield and reliability improvement of embedded memories. ASICON (2015)
Daisuke Suga, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Electrical interconnect test method of 3D ICs by injected charge volume. 3DIC (2015)
Yi-Wei Ma, Jiann-Liang Chen, Ching-Hesign Chou, Shyue-Kung Lu
A Power Saving Mechanism for Multimedia Streaming Services in Cloud Computing. IEEE Syst. J. 8 (1) (2014)
Masaki Hashizume, Shoichi Umezu, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
A built-in supply current test circuit for electrical interconnect tests of 3D ICs. 3DIC (2014)
Shyue-Kung Lu, Huai-Min Li, Masaki Hashizume, Jin-Hua Hong, Zheng-Ru Tsai
Efficient test length reduction techniques for interposer-based 2.5D ICs. VLSI-DAT (2014)
Shyue-Kung Lu, Hao-Cheng Jheng, Hao-Wei Lin, Masaki Hashizume, Seiji Kajihara
Built-In Scrambling Analysis for Yield Enhancement of Embedded Memories. ATS (2014)
Shyue-Kung Lu, Hao-Cheng Jheng, Masaki Hashizume, Jiun-Lang Huang, Pony Ning
Fault Scrambling Techniques for Yield Enhancement of Embedded Memories. Asian Test Symposium (2013)
Tsu-Lin Li, Masaki Hashizume, Shyue-Kung Lu
An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs. IEICE Trans. Inf. Syst. (9) (2013)
Masaki Hashizume, Tomoaki Konishi, Hiroyuki Yotsuyanagi, Shyue-Kung Lu
Testable Design for Electrical Testing of Open Defects at Interconnects in 3D ICs. Asian Test Symposium (2013)
Shyue-Kung Lu, Huan-Hua Huang, Jiun-Lang Huang, Pony Ning
Synergistic Reliability and Yield Enhancement Techniques for Embedded SRAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (1) (2013)
Shyue-Kung Lu, Uang-Chang Lu, Seng-Wen Pong, Hao-Cheng Cheng
Efficient test and repair architectures for 3D TSV-based random access memories. VLSI-DAT (2013)
Shyue-Kung Lu, Ming-Chang Chen, Yen-Chi Chen
Error-tolerance evaluation and design techniques for motion estimation computing arrays. IOLTS (2013)
Shyue-Kung Lu, Tin-Wei Chang, Han-Yu Hsu
Yield enhancement techniques for 3-dimensional random access memories. Microelectron. Reliab. 52 (6) (2012)
Shyue-Kung Lu, Zhen-Yu Wang, Yi-Ming Tsai, Jiann-Liang Chen
Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31 (4) (2012)
Shyue-Kung Lu, Tsu-Lin Li, Pony Ning
Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs. Asian Test Symposium (2012)
Shyue-Kung Lu, Ya-Chen Huang
Improving Reusability of Test Symbols for Test Data Compression. J. Inf. Sci. Eng. 28 (2) (2012)
Cheng-Wen Wu, Shyue-Kung Lu, Jin-Fu Li
On test and repair of 3D random access memory. ASP-DAC (2012)
Shyue-Kung Lu, Yin Chen, Shi-Yu Huang, Cheng Wu
Speeding Up Emulation-Based Diagnosis Techniques for Logic Cores. IEEE Des. Test Comput. 28 (4) (2011)
Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. IEEE Trans. Very Large Scale Integr. Syst. 18 (2) (2010)
Zhen-Yu Wang, Yi-Ming Tsai, Shyue-Kung Lu
Built-In Self-Repair Techniques for Heterogeneous Memory Cores. PRDC (2009)
Shyue-Kung Lu, Yuang-Cheng Hsiao, Chia-Hsiu Liu, Chun-Lin Yang
Low-Power Built-In Self-Test Techniques for Embedded SRAMs. VLSI Design 2007 (2007)
Chun-Lin Yang, Yuang-Cheng Hsiao, Shyue-Kung Lu
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. PRDC (2007)
Shyue-Kung Lu, Chih-Hsien Hsu
Fault tolerance techniques for high capacity RAM. IEEE Trans. Reliab. 55 (2) (2006)
Ming-Wei Wu, Yennun Huang, Ing-Yi Chen, Shyue-Kung Lu, Sy-Yen Kuo
A Scalable Port Forwarding for P2P-Based Wi-Fi Applications. WASA (2006)
Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu
Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits. PRDC (2006)
Shyue-Kung Lu, Yu-Chen Tsai, Chih-Hsien Hsu, Kuo-Hua Wang, Cheng-Wen Wu
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy. IEEE Trans. Very Large Scale Integr. Syst. 14 (1) (2006)
Shyue-Kung Lu, Chun-Lin Yang, Han-Wen Lin
Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy. ACIS-ICIS (2006)
Shyue-Kung Lu, Yu-Cheng Tsai, Shih-Chang Huang
A BIRA algorithm for embedded memories with 2D redundancy. MTDT (2005)
Ming-Wei Wu, Yennun Huang, Shyue-Kung Lu, Ing-Yi Chen, Sy-Yen Kuo
A Multi-Faceted Approach towards Spam-Resistible Mail. PRDC (2005)
Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang
Design-for-testability and fault-tolerant techniques for FFT processors. IEEE Trans. Very Large Scale Integr. Syst. 13 (6) (2005)
Shyue-Kung Lu
Defect Level Prediction Using Multi-Model Fault Coverage. IEICE Trans. Inf. Syst. (6) (2004)
Shyue-Kung Lu, Chien-Hung Yeh, Han-Wen Lin
Efficient Built-in Self-Test Techniques for Memory-Based FFT Processors. PRDC (2004)
Shyue-Kung Lu, Mau-Jung Lu
Enhancing Delay Fault Testability for FIR Filters Based on Realistic Sequential Cell Fault Model. DELTA (2004)
Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai
Testing and Diagnosis Techniques for LUT-Based FPGA's. Asian Test Symposium (2004)
Shyue-Kung Lu, Shih-Chang Huang
Built-in Self-Test and Repair (BISTR) Techniques for Embedded RAMs. MTDT (2004)
Shyue-Kung Lu, Jian-Long Chen, Cheng-Wen Wu, Ken-Feng Chang, Shi-Yu Huang
Combinational circuit fault diagnosis using logic emulation. ISCAS (5) (2003)
Shyue-Kung Lu
A Novel Built-In Self-Repair Approach for Embedded RAMs. J. Electron. Test. 19 (3) (2003)
Hong-Chou Kao, Ming-Fu Tsai, Shi-Yu Huang, Cheng-Wen Wu, Wen-Feng Chang, Shyue-Kung Lu
Efficient Double Fault Diagnosis for CMOS Logic Circuits With a Specific Application to Generic Bridging Faults. J. Inf. Sci. Eng. 19 (4) (2003)
Shyue-Kung Lu, Chien-Hung Yeh
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. Asian Test Symposium (2002)
Shyue-Kung Lu, Chien-Hung Yeh
Enhancing Delay Fault Testability for Iterative Logic Array. PRDC (2002)
Chih-Hsien Hsu, Shyue-Kung Lu
Fault-tolerance design of memory systems based on DBL structures. APCCAS (1) (2002)
Fu-Min Yeh, Shyue-Kung Lu, Sy-Yen Kuo
OBDD-based evaluation of k-terminal network reliability. IEEE Trans. Reliab. 51 (4) (2002)
Shyue-Kung Lu, Fu-Min Yeh, Jen-Sheng Shih
Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs. VLSI Design 2002 (1) (2002)
Shyue-Kung Lu, Chung-Yang Chen
Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's. Asian Test Symposium (2002)
Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
A Profit Evaluation System (PES) for logic cores at early design stage. ICECS (2001)
Shyue-Kung Lu, Chih-Hsien Hsu
Built-In self-repair for divided word line memory. ISCAS (4) (2001)
Chih-Hsien Hsu, Shyue-Kung Lu, Sy-Yen Kuo
Novel Fault-Tolerant Techniques for High Capacity RAMs. PRDC (2001)
Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
Built-in self-test and fault diagnosis for lookup table FPGAs. ISCAS (2000)
Shyue-Kung Lu, Jen-Sheng Shih, Cheng-Wen Wu
A Testable/Fault Tolerant FFT Processor Design. Asian Test Symposium (2000)
Shyue-Kung Lu, Jen-Sheng Shih
Testing Configurable LUT-Based FPGAs. J. Inf. Sci. Eng. 16 (5) (2000)
Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu
Defect Level Prediction Using Multi-Model Fault Coverage. Asian Test Symposium (1999)
Shyue-Kung Lu, Cheng-Wen Wu
A novel approach to testing LUT-based FPGAs. ISCAS (1) (1999)
Shyue-Kung Lu, Sy-Yen Kuo, Cheng-Wen Wu
Fault-Tolerant Interleaved Memory Systems with Two-Level Redundancy. IEEE Trans. Computers 46 (9) (1997)
Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang
Cell delay fault testing for iterative logic arrays. J. Electron. Test. 9 (3) (1996)
Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu
C-testable design techniques for iterative logic arrays. IEEE Trans. Very Large Scale Integr. Syst. 3 (1) (1995)
Cheng-Wen Wu, Shyue-Kung Lu
Designing Self-Testable Cellular Arrays. ICCD (1991)