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Open Defect Detection with a Built-in Test Circuit by IDDT Appearance Time in CMOS ICs.
Ayumu Kambara
Hiroyuki Yotsuyanagi
Daichi Miyoshi
Masaki Hashizume
Shyue-Kung Lu
Published in:
ATS (2017)
Keyphrases
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defect detection
circuit design
high speed
analog vlsi
feature extraction
delay insensitive
low voltage
test data
appearance model
vlsi circuits
statistical tests
appearance cues
low cost
bounding box
cmos technology