Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits.

Kazuya Shimizu Noriyoshi Itazaki Kozo Kinoshita

Published in: Asian Test Symposium (2002)

Keyphrases

high speed
simulation model
simulation environment
fault diagnosis
simulation models
mathematical model
power consumption
fault detection
reduction method
fault model
power reduction
information systems
analog circuits