Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits.
Seiji KajiharaIrith PomeranzKozo KinoshitaSudhakar M. ReddyPublished in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (1995)
Keyphrases
- cost effective
- logic circuits
- test set
- low power
- low cost
- test cases
- error rate
- training set
- functional decomposition
- test data
- cost effectiveness
- fault diagnosis
- tunnel diode
- high speed
- logic synthesis
- gate array
- training data
- neural network
- training and test sets
- real time
- digital signal processing
- power dissipation
- random selection
- power consumption
- data sets