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On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout.
Sudhakar M. Reddy
Irith Pomeranz
Huaxing Tang
Seiji Kajihara
Kozo Kinoshita
Published in:
ITC (2002)
Keyphrases
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logic circuits
low power
power dissipation
high speed
tunnel diode
functional decomposition
power consumption
low cost
logic synthesis
interconnection networks
gate array
software development life cycle
wireless sensor networks
computer vision
energy consumption
pattern matching
real time