Hideyuki Ichihara

Publication Activity (10 Years)

Years Active: 1997-2023
Publications (10 Years): 10

Top Topics

Top Venues

Publications

Naoki Okuda, Kaori Maeda, Chisa Takano, Hideyuki Ichihara
A Resource Estimation Method in Multi-Cloud Environment with a Model Based on a Repairable-Item Inventory System. COMPSAC (2023)
Tamaki Kozuma, Qilin Wang, Hideyuki Ichihara, Tomoo Inoue
Reliability Analysis of Approximate Multipliers with Recovery Schemes. ATS (2023)
Hideyuki Ichihara, Naruki Itoh, Tomoo Inoue
An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing Application. ITC-Asia (2022)
Hideyuki Ichihara, Kazunori Yukihiro, Tomoo Inoue
A Design of Approximate Voting Schemes for Fail-Operational Systems. ATS (2021)
Hideyuki Ichihara, Takayuki Fukuda, Tomoo Inoue
A Design of Reliable Linear FSMs with Equivalent States in Stochastic Computing. DFT (2021)
Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue
Transient Fault Tolerant State Assignment for Stochastic Computing Based on Linear Finite State Machines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2020)
Hideyuki Ichihara, Yuki Maeda, Tsuyoshi Iwagaki, Tomoo Inoue
State Encoding with Stochastic Numbers for Transient Fault Tolerant Linear Finite State Machines. DFT (2019)
Tsuyoshi Iwagaki, Sho Yuasa, Hideyuki Ichihara, Tomoo Inoue
An Empirical Approach to RTL Scan Path Design Focusing on Structural Interpretation in Logic Synthesis. ITC-Asia (2019)
Hideyuki Ichihara, Tatsuyoshi Sugino, Shota Ishii, Tsuyoshi Iwagaki, Tomoo Inoue
Compact and Accurate Digital Filters Based on Stochastic Computing. IEEE Trans. Emerg. Top. Comput. 7 (1) (2019)
Hideyuki Ichihara, Motoi Fukuda, Tsuyoshi Iwagaki, Tomoo Inoue
State assignment for fault tolerant stochastic computing with linear finite state machines. ITC-Asia (2017)
Hideyuki Ichihara, Tomoya Inaoka, Tsuyoshi Iwagaki, Tomoo Inoue
Logic simplification by minterm complement for error tolerant application. ICCD (2015)
Tsuyoshi Iwagaki, Yutaro Ishimori, Hideyuki Ichihara, Tomoo Inoue
Designing area-efficient controllers for multi-cycle transient fault tolerant systems. ETS (2015)
Yuki Fukazawa, Hideyuki Ichihara, Tomoo Inoue
A fault tolerant response analyzer with self-error-correction capability. ETS (2015)
Hideyuki Ichihara, Junpei Kamei, Tsuyoshi Iwagaki, Tomoo Inoue
A practical approach for logic simplification based on fault acceptability for error tolerant application. ETS (2015)
Tsuyoshi Iwagaki, Tatsuya Nakaso, Ryoko Ohkubo, Hideyuki Ichihara, Tomoo Inoue
Scheduling algorithm in datapath synthesis for long duration transient fault tolerance. DFT (2014)
Hideyuki Ichihara, Shota Ishii, Daiki Sunamori, Tsuyoshi Iwagaki, Tomoo Inoue
Compact and accurate stochastic circuits with shared random number sources. ICCD (2014)
Yuki Fukazawa, Tsuyoshi Iwagaki, Hideyuki Ichihara, Tomoo Inoue
A Transient Fault Tolerant Test Pattern Generator for On-line Built-in Self-Test. Asian Test Symposium (2013)
Hideyuki Ichihara, Noboru Shimizu, Tsuyoshi Iwagaki, Tomoo Inoue
Modeling economics of LSI design and manufacturing for test design selection. ICCD (2012)
Tsuyoshi Iwagaki, Takehiro Mikami, Hideyuki Ichihara, Tomoo Inoue
Utilizing register transfer level false paths for circuit optimization with a logic synthesis tool. APCCAS (2012)
Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue
Test Compression Based on Lossy Image Encoding. Asian Test Symposium (2011)
Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara
High-level synthesis for multi-cycle transient fault tolerant datapaths. IOLTS (2011)
Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue
Hybrid Test Application in Partial Skewed-Load Scan Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue
An FPGA-based fail-soft system with adaptive reconfiguration. IOLTS (2010)
Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic. DELTA (2010)
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
Design and Optimization of Transparency-Based TAM for SoC Test. IEICE Trans. Inf. Syst. (6) (2010)
Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue
Hybrid test application in hybrid delay scan design. ETS (2010)
Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue
A Practical Threshold Test Generation for Error Tolerant Application. IEICE Trans. Inf. Syst. (10) (2010)
Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue
A Practical Approach to Threshold Test Generation for Error Tolerant Circuits. Asian Test Symposium (2009)
Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue
Reliability and Performance Analysis of FPGA-Based Fault Tolerant System. DFT (2009)
Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara
A Self-Test of Dynamically Reconfigurable Processors with Test Frames. IEICE Trans. Inf. Syst. (3) (2008)
Hideyuki Ichihara, Tomoyuki Saiki, Tomoo Inoue
An Architecture of Embedded Decompressor with Reconfigurability for Test Compression. IEICE Trans. Inf. Syst. (3) (2008)
Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara
TAM Design and Optimization for Transparency-Based SoC Test. VTS (2007)
Hideyuki Ichihara, Yukinori Setohara, Yusuke Nakashima, Tomoo Inoue
Test Compression / Decompression Based on JPEG VLC Algorithm. ATS (2007)
Tomoo Inoue, Takashi Fujii, Hideyuki Ichihara
Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors. ETS (2007)
Hideyuki Ichihara, Toshihiro Ohara, Michihiro Shintani, Tomoo Inoue
A Variable-Length Coding Adjustable for Compressed Test Application. IEICE Trans. Inf. Syst. (8) (2007)
Hideyuki Ichihara, Toshimasa Kuchii, Masaaki Yamadate, Hideaki Sakaguchi, Hiroshi Uemura, Kozo Kinoshita
A statistical error model for image sensors and its testing. Systems and Computers in Japan 38 (11) (2007)
Tomoyuki Saiki, Hideyuki Ichihara, Tomoo Inoue
A Reconfigurable Embedded Decompressor for Test Compression. DELTA (2006)
Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
An Adaptive Decompressor for Test Application with Variable-Length Coding. Inf. Media Technol. 1 (2) (2006)
Hideyuki Ichihara, Michihiro Shintani, Tomoo Inoue
Huffman-Based Test Response Coding. IEICE Trans. Inf. Syst. (1) (2005)
Yoshinobu Higami, Seiji Kajihara, Hideyuki Ichihara, Yuzo Takamatsu
Test cost reduction for logic circuits: Reduction of test data volume and test application time. Systems and Computers in Japan 36 (6) (2005)
Michihiro Shintani, Toshihiro Ohara, Hideyuki Ichihara, Tomoo Inoue
A Huffman-based coding with efficient test application. ASP-DAC (2005)
Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara
An Effective Design for Hierarchical Test Generation Based on Strong Testability. Asian Test Symposium (2005)
Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue
A Test Decompression Scheme for Variable-Length Coding. Asian Test Symposium (2004)
Hideyuki Ichihara, Tomoo Inoue
A Method of Test Generation for Acyclic Sequential Circuits Using Single Stuck-at Fault Combinational ATPG. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Hideyuki Ichihara, Kozo Kinoshita, Koji Isodono, Shigeki Nishikawa
Channel Width Test Data Compression under a Limited Number of Test Inputs and Outputs. VLSI Design (2003)
Hideyuki Ichihara, Tomoo Inoue
Test Generation for Acyclic Sequential Circuits with Single Stuck-at Fault Combinational ATPG. DATE (2003)
Hideyuki Ichihara, Michihiro Shintani, Toshihiro Ohara, Tomoo Inoue
Test Response Compression Based on Huffman Coding. Asian Test Symposium (2003)
Hideyuki Ichihara, Tomoo Inoue
Generating Small Test Sets for Test Compression/Decompression Scheme Using Statistical Coding. DELTA (2002)
Hideyuki Ichihara, Atsuhiro Ogawa, Tomoo Inoue, Akio Tamura
Dynamic Test Compression Using Statistical Coding. Asian Test Symposium (2001)
Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy
Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design (2000)
Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On Test Generation with A Limited Number of Tests. Great Lakes Symposium on VLSI (1999)
Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. Asian Test Symposium (1999)
Hideyuki Ichihara, Seiji Kajihara, Kozo Kinoshita
An Efficient Procedure for Obtaining Implication Relations and Its Application to Redundancy Identification. Asian Test Symposium (1998)
Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara
On invariant implication relations for removing partial circuits. Systems and Computers in Japan 28 (7) (1997)
Hideyuki Ichihara, Kozo Kinoshita
On Acceleration of Logic Circuits Optimization Using Implication Relations. Asian Test Symposium (1997)