Yuki Yoshikawa

Publication Activity (10 Years)

Years Active: 2005-2015
Publications (10 Years): 0

Top Topics

Learning Algorithm

Injection Lasers

Expectation Maximization

Top Venues

Publications

Ken Takano, Hideitsu Hino, Yuki Yoshikawa, Noboru Murata
Patchworking Multiple Pairwise Distances for Learning with Distance Matrices. LVA/ICA (2015)
Yuki Yoshikawa
A binding algorithm in high-level synthesis for path delay testability. ASP-DAC (2013)
Yuki Yoshikawa, Daisuke Iwai, Kosuke Sato
A study of thermal sensation with visuo-thermal projection interfaces. GCCE (2013)
Hideyuki Ichihara, Yuka Iwamoto, Yuki Yoshikawa, Tomoo Inoue
Test Compression Based on Lossy Image Encoding. Asian Test Symposium (2011)
Tomoo Inoue, Hayato Henmi, Yuki Yoshikawa, Hideyuki Ichihara
High-level synthesis for multi-cycle transient fault tolerant datapaths. IOLTS (2011)
Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue
Hybrid Test Application in Partial Skewed-Load Scan Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2011)
Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue
An FPGA-based fail-soft system with adaptive reconfiguration. IOLTS (2010)
Tomoo Inoue, Nobukazu Izumi, Yuki Yoshikawa, Hideyuki Ichihara
A Fast Threshold Test Generation Algorithm Based on 5-Valued Logic. DELTA (2010)
Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue
Hybrid test application in hybrid delay scan design. ETS (2010)
Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue
A Practical Threshold Test Generation for Error Tolerant Application. IEICE Trans. Inf. Syst. (10) (2010)
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification. VTS (2009)
Hideyuki Ichihara, Kenta Sutoh, Yuki Yoshikawa, Tomoo Inoue
A Practical Approach to Threshold Test Generation for Error Tolerant Circuits. Asian Test Symposium (2009)
Ryoji Noji, Satoshi Fujie, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue
Reliability and Performance Analysis of FPGA-Based Fault Tolerant System. DFT (2009)
Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara
Fast false path identification based on functional unsensitizability using RTL information. ASP-DAC (2009)
Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara
False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults. ATS (2007)
Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
Design for Testability Based on Single-Port-Change Delay Testing for Data Paths. Asian Test Symposium (2005)