Masahiro Numa

Publication Activity (10 Years)

Years Active: 1995-2024
Publications (10 Years): 24

Top Topics

Convolutional Neural Networks

Top Venues

IEICE Trans. Fundam. Electron. Commun. Comput. Sci.

IEICE Electron. Express

Publications

Tomohiro Nishiguchi, Nobutaka Kuroki, Masahiro Numa
Technology Remapping Approach Using Multi-Gate Reconfigurable Cells for Post-Mask Functional ECO. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107 (3) (2024)
Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa
Multi-Category Image Super-Resolution with Convolutional Neural Network and Multi-Task Learning. IEICE Trans. Inf. Syst. (1) (2021)
Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
A 35-mV supply ring oscillator consisting of stacked body bias inverters for extremely low-voltage LSIs. IEICE Electron. Express 18 (6) (2021)
Masaya Nishi, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Hikaru Sebe, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
A 34-mV Startup Ring Oscillator Using Stacked Body Bias Inverters for Extremely Low-Voltage Thermoelectric Energy Harvesting. NEWCAS (2020)
Kazuya Urazoe, Nobutaka Kuroki, Yu Kato, Shinya Ohtani, Tetsuya Hirose, Masahiro Numa
Improvement of Luminance Isotropy for Convolutional Neural Networks-Based Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (7) (2020)
Kaori Matsumoto, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
An 11.8 nA ultra-low power active diode using a hysteresis common gate comparator for low-power energy harvesting systems. IEICE Electron. Express 17 (11) (2020)
Kunihiko Taya, Nobutaka Kuroki, Naoto Takeda, Tetsuya Hirose, Masahiro Numa
Detecting tampered regions in JPEG images via CNN. NEWCAS (2020)
Masaya Nishi, Yuichiro Nakazawa, Kaori Matsumoto, Nobutaka Kuroki, Masahiro Numa, Ryo Matsuzuka, Osamu Maida, Daisuke Kanemoto, Tetsuya Hirose
Sub-0.1V Input, Low-Voltage CMOS Driver Circuit for Multi-Stage Switched Capacitor Voltage Boost Converter. ICECS (2019)
Kaori Matsumoto, Tetsuya Hirose, Hiroki Asano, Yuto Tsuji, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa
An ultra-low power active diode using a hysteresis common gate comparator for low-voltage and low-power energy harvesting systems. VLSI-SoC (2018)
Yuichiro Nakazawa, Tetsuya Hirose, Toshihiro Ozaki, Yuto Tsuji, Shuto Kanzaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
Analytical Study of Multi-stage Switched-Capacitor Voltage Boost Converter for Ultra-low Voltage Energy Harvesting. ISCAS (2018)
Shuto Kanzaki, Tetsuya Hirose, Hiroki Asano, Yuichiro Nakazawa, Nobutaka Kuroki, Masahiro Numa
Switched-Capacitor Voltage Buck Converter with Step-Down-Ratio and Clock-Frequency Controllers for Ultra-Low-Power IoT Devices. ICECS (2018)
Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
A Sub-1-µs Start-Up Time, Fully-Integrated 32-MHz Relaxation Oscillator for Low-Power Intermittent Systems. IEICE Trans. Electron. (3) (2018)
Shinya Ohtani, Yu Kato, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa
Multi-Channel Convolutional Neural Networks for Image Super-Resolution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2) (2017)
Hiroki Asano, Tetsuya Hirose, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
An area-efficient, 0.022-mm2, fully integrated resistor-less relaxation oscillator for ultra-low power real-time clock applications. ISCAS (2017)
Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Kyohei Shinonaga, Nobutaka Kuroki, Masahiro Numa
An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2017)
Yuto Tsuji, Tetsuya Hirose, Toshihiro Ozaki, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
A 0.1-0.6 V input range voltage boost converter with low-leakage driver for low-voltage energy harvesting. ICECS (2017)
Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
Sub-1-μs start-up time, 32-MHz relaxation oscillator for low-power intermittent VLSI systems. ASP-DAC (2017)
Takanori Sato, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
An ultra-low-power supercapacitor voltage monitoring system for low-voltage energy harvesting. ICECS (2017)
Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
A 0.38-μW stand-by power, 50-nA-to-1-mA load current range DC-DC converter with self-biased linear regulator for ultra-low power battery management. A-SSCC (2016)
Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting. IEEE J. Solid State Circuits 51 (10) (2016)
Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
A Highly Efficient Switched-Capacitor Voltage Boost Converter with Nano-Watt MPPT Controller for Low-Voltage Energy Harvesting. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2016)
Hiroki Asano, Tetsuya Hirose, Keishi Tsubaki, Taro Miyoshi, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability. ESSCIRC (2016)
Hiroki Asano, Tetsuya Hirose, Taro Miyoshi, Keishi Tsubaki, Toshihiro Ozaki, Nobutaka Kuroki, Masahiro Numa
A fully integrated, 1-µs start-up time, 32-MHz relaxation oscillator for low-power intermittent systems. NEWCAS (2016)
Yu Kato, Shinya Ohtani, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa
Image super-resolution with multi-channel convolutional neural networks. NEWCAS (2016)
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. IEICE Electron. Express 12 (4) (2015)
Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
A 32-kHz Real-Time Clock Oscillator with On-Chip PVT Variation Compensation Circuit for Ultra-Low Power MCUs. IEICE Trans. Electron. (5) (2015)
Ryo Matsuzuka, Tetsuya Hirose, Yuzuru Shizuku, Nobutaka Kuroki, Masahiro Numa
A 0.19-V minimum input low energy level shifter for extremely low-voltage VLSIs. ISCAS (2015)
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated 3-terminal voltage converter with MPPT for low-voltage energy harvesters. ASP-DAC (2015)
Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa
A fully-integrated, high-conversion-ratio and dual-output voltage boost converter with MPPT for low-voltage energy harvesting. A-SSCC (2015)
Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa
A Fully On-Chip, 6.66-kHz, 320-nA, 56ppm/°C, CMOS Relaxation Oscillator with PVT Variation Compensation Circuit. IEICE Trans. Electron. (6) (2014)
Toshihiro Ozaki, Tetsuya Hirose, Takahiro Nagai, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
A 0.21-V minimum input, 73.6% maximum efficiency, fully integrated voltage boost converter with MPPT for low-voltage energy harvesters. ESSCIRC (2014)
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. NEWCAS (2014)
Keishi Tsubaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
A 32.55-kHz, 472-nW, 120ppm/°C, fully on-chip, variation tolerant CMOS relaxation oscillator for a real-time clock application. ESSCIRC (2013)
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
1.2-V Supply, 100-nW, 1.09-V Bandgap and 0.7-V Supply, 52.5-nW, 0.55-V Subbandgap Reference Circuits for Nanowatt CMOS LSIs. IEEE J. Solid State Circuits 48 (6) (2013)
Yumiko Tsuruya, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa, Osamu Kobayashi
A nano-watt power CMOS amplifier with adaptive biasing for power-aware analog LSIs. ESSCIRC (2012)
Keishi Tsubaki, Tetsuya Hirose, Yuji Osaki, Seiichiro Shiga, Nobutaka Kuroki, Masahiro Numa
A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator. ICECS (2012)
Yuji Osaki, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
A low-power single-slope analog-to-digital converter with digital PVT calibration. ICECS (2012)
Masahiro Numa
FOREWORD. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2012)
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs. IEEE J. Solid State Circuits 47 (7) (2012)
Yuji Osaki, Tetsuya Hirose, Kei Matsumoto, Nobutaka Kuroki, Masahiro Numa
Robust Subthreshold CMOS Digital Circuit Design with On-Chip Adaptive Supply Voltage Scaling Technique. IEICE Trans. Electron. (1) (2011)
Kosuke Isono, Tetsuya Hirose, Keishi Tsubaki, Nobutaka Kuroki, Masahiro Numa
A 18.9-nA standby current comparator with adaptive bias current generator. A-SSCC (2011)
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder. ASP-DAC (2011)
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs. ESSCIRC (2011)
Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
A wide input voltage range level shifter circuit for extremely low-voltage digital LSIs. IEICE Electron. Express 8 (12) (2011)
Kei Matsumoto, Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa
Subthreshold SRAM with Write Assist Technique Using On-Chip Threshold Voltage Monitoring Circuit. IEICE Trans. Electron. (6) (2011)
Shingo Chikamatsu, Tomohiro Nakaya, Masakazu Kouda, Nobutaka Kuroki, Tetsuya Hirose, Masahiro Numa
Super-resolution technique for thermography with dual-camera system. ISCAS (2010)
Tetsuya Hirose, Yuji Osaki, Nobutaka Kuroki, Masahiro Numa
A nano-ampere current reference circuit and its temperature dependence control by using temperature characteristics of carrier mobilities. ESSCIRC (2010)
Kosuke Shioki, Narumi Okada, Kosuke Watanabe, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
An Error Diagnosis Technique Based on Clustering of Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2010)
Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi
control. IEICE Electron. Express 6 (8) (2009)
Kosuke Shioki, Narumi Okada, Toshiro Ishihara, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa
An Error Diagnosis Technique Based on Location Sets to Rectify Subcircuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2009)
Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa
Delayed-ABC SOI for crosstalk noise repair. IEICE Electron. Express 5 (9) (2008)
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation. J. Comput. 3 (5) (2008)
Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. VLSI Design (2007)
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation. IEICE Trans. Electron. (4) (2007)
Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa
Charge recycling in MTCMOS circuits with block dividing. IEICE Electron. Express 4 (18) (2007)
Akira Tada, Hiromi Notani, Masahiro Numa
A novel power gating scheme with charge recycling. IEICE Electron. Express 3 (12) (2006)
Masayuki Kitamura, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Hiromi Notani, Akira Tada, Shigeto Maegawa
High Performance CMOS Circuit by Using Charge Recycling Active Body-Bias Controlled SOI. PATMOS (2006)
Nobutaka Kuroki, Nobuhiro Oka, Masahiro Numa, Keisuke Yamamoto
An Evaluation of Triple Density Error Diffusion for Medical Monochrome LCDs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (6) (2006)
Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi
Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI. IEICE Electron. Express 3 (21) (2006)
Nobutaka Kuroki, Takahiro Manabe, Masahiro Numa
Adaptive arithmetic coding for image prediction errors. ISCAS (3) (2004)
Masaaki Iijima, Katsuya Fujita, Kazuki Fukuoka, Masahiro Numa, Keisuke Yamamoto, Kengo Takata
A technique for high-speed circuits on SOI using look-ahead type active body bias control. ISCAS (2) (2004)
Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada
Leakage power reduction for clock gating scheme on PD-SOI. ISCAS (2) (2004)
Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. PATMOS (2004)
Hiroshi Inoue, Takahiro Iwasaki, Toshifumi Sugane, Masahiro Numa, Keisuke Yamamoto
Application of Error Diagnosis Technique to Incremental Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2003)
Hirokazu Masuda, Nobutaka Kuroki, Masahiro Numa, Kotaro Hirano
Layered blind deconvolution with interband prediction. Systems and Computers in Japan 31 (3) (2000)
Atsushi Yoshikawa, Seiji Kajihara, Masahiro Numa, Kozo Kinoshita
A diagnosis method for single logic design errors in gate-level combinational circuits. Systems and Computers in Japan 28 (6) (1997)
Changzheng Wang, Masahiro Numa, Kotaro Hirano
ATM data transmission systems based on N-ISDN. IEEE Trans. Commun. 43 (2/3/4) (1995)