A 95-nA, 523ppm/°C, 0.6-μW CMOS current reference circuit with subthreshold MOS resistor ladder.
Yuji OsakiTetsuya HiroseNobutaka KurokiMasahiro NumaPublished in: ASP-DAC (2011)
Keyphrases
- low voltage
- high speed
- cmos technology
- floating gate
- circuit design
- design considerations
- analog vlsi
- vlsi circuits
- random access memory
- compression algorithm
- low power
- delay insensitive
- bayesian network classifiers
- power management
- data mining
- bayesian classifier
- parallel processing
- power consumption
- low cost
- image processing