A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs.
Yuji OsakiTetsuya HiroseNobutaka KurokiMasahiro NumaPublished in: ESSCIRC (2011)
Keyphrases
- low voltage
- error correction
- random access memory
- cmos technology
- mixed signal
- design considerations
- power line
- error correcting
- digital circuits
- circuit design
- error detection
- low power
- channel coding
- delay insensitive
- power management
- error detection and correction
- leakage current
- multi valued
- low cost
- metal oxide semiconductor
- chip design
- magnetic tape
- error control
- asynchronous circuits
- parallel processing