Mitsuji Okada

Publication Activity (10 Years)

Years Active: 2000-2023
Publications (10 Years): 7

Top Topics

Asynchronous Circuits

Transmission Line

Matrix Multiplication

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEICE Electron. Express

Publications

Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 70 (9) (2023)
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. IEEE J. Solid State Circuits 58 (7) (2023)
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. HCS (2022)
Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. NEWCAS (2022)
Tomoya Arakawa, Joshin Sone, Mitsuji Okada, Mototsugu Hamada, Tadahiro Kuroda
Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. ISCAS (2019)
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. IEICE Electron. Express 12 (4) (2015)
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2015)
Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. NEWCAS (2014)
Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno
A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. IEEE J. Solid State Circuits 47 (2) (2012)
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. IEEE J. Solid State Circuits 45 (12) (2010)
Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi
A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. ISSCC (2010)
Shinichi Kozu, Toshiya Aramaki, Chinatsu Ikeda, Yasuaki Kuroda, Satoru Kawanago, Mitsuji Okada, Hiroshi Kariya, Masao Manabe, Hirotaka Utani, Eiji Sudou, Yukihiro Oda, Hideo Suzukii
A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home. CICC (2000)