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An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs.
Yuzuru Shizuku
Tetsuya Hirose
Nobutaka Kuroki
Masahiro Numa
Mitsuji Okada
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2015)
Keyphrases
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ultra low power
low power
circuit design
flip flops
high speed
low cost
power consumption
power dissipation
cmos image sensor
image sequences
sensor networks
parallel processing
efficient implementation
cmos technology
mixed signal