Leakage power reduction for clock gating scheme on PD-SOI.

Kazuki Fukuoka Masaaki Iijima Kenji Hamada Masahiro Numa Akira Tada

Published in: ISCAS (2) (2004)

Keyphrases

power reduction
power consumption
low power
power saving
clock gating
power dissipation
high speed
low cost
operating system