A 6.66-kHz, 940-nW, 56ppm/°C, fully on-chip PVT variation tolerant CMOS relaxation oscillator.
Keishi TsubakiTetsuya HiroseYuji OsakiSeiichiro ShigaNobutaka KurokiMasahiro NumaPublished in: ICECS (2012)
Keyphrases
- analog vlsi
- high speed
- circuit design
- low cost
- cmos image sensor
- single chip
- chip design
- cmos technology
- low power
- image sensor
- focal plane
- random access memory
- power consumption
- nm technology
- high density
- power dissipation
- probabilistic relaxation
- mixed signal
- differential equations
- ultra low power
- low voltage
- low power consumption
- image segmentation
- power supply
- vlsi circuits
- iterative algorithms
- compression algorithm