Takashi Ipposhi

Publication Activity (10 Years)

Years Active: 2005-2009
Publications (10 Years): 0

Publications

Kayoko Seto, Masaaki Iijima, Tetsuya Hirose, Masahiro Numa, Akira Tada, Takashi Ipposhi
control. IEICE Electron. Express 6 (8) (2009)
Akira Tada, Hiromi Notani, Genichi Tanaka, Toshiaki Iwamatsu, Takashi Ipposhi, Masayuki Terai, Masaaki Iijima, Masahiro Numa
Delayed-ABC SOI for crosstalk noise repair. IEICE Electron. Express 5 (9) (2008)
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation. J. Comput. 3 (5) (2008)
Mitsuo Usami, Hisao Tanabe, Akira Sato, Isao Sakama, Yukio Maki, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue
A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory. ISSCC (2007)
Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42 (4) (2007)
Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi
Ultra Low Voltage Operation with Bootstrap Scheme for Single Power Supply SOI-SRAM. VLSI Design (2007)
Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
Look-Ahead Dynamic Threshold Voltage Control Scheme for Improving Write Margin of SOI-7T-SRAM. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (12) (2007)
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42 (11) (2007)
Fukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOI. IEICE Trans. Electron. (4) (2007)
Masaaki Iijima, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi, Shigeto Maegawa
Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation. IEICE Trans. Electron. (4) (2007)
Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa
Charge recycling in MTCMOS circuits with block dividing. IEICE Electron. Express 4 (18) (2007)
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka
A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOI. CICC (2006)
Masaaki Iijima, Kenji Hamada, Masayuki Kitamura, Masahiro Numa, Akira Tada, Takashi Ipposhi
Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI. IEICE Electron. Express 3 (21) (2006)
Fukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto
A capacitorless twin-transistor random access memory (TTRAM) on SOI. CICC (2005)