Hiroki Shimano

Publication Activity (10 Years)

Years Active: 1996-2009
Publications (10 Years): 0

Publications

Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform. IEICE Trans. Electron. (3) (2009)
Hiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto
A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC Platform. IEICE Trans. Electron. (10) (2007)
Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto
A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory. IEEE J. Solid State Circuits 42 (4) (2007)
Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi
A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. IEEE J. Solid State Circuits 42 (11) (2007)
Ken'ichi Shimomura, Hiroki Shimano, Narumi Sakashita, Fumihiro Okuda, Toshiyuki Oashi, Yasuo Yamaguchi, Takahisa Eimori, Masahide Inuishi, Kazutami Arimoto, Shigeto Maegawa, Yasuo Inoue, Shinji Komori, Kazuo Kyuma
A 1-V 46-ns 16-Mb SOI-DRAM with body control technique. IEEE J. Solid State Circuits 32 (11) (1997)
Narumi Sakashita, Fumihiro Okuda, Ken'ichi Shimomura, Hiroki Shimano, Mitsuhiro Hamada, Tetsuo Tada, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. ITC (1996)
Narumi Sakashita, Yasuhiko Nitta, Ken'ichi Shimomura, Fumihiro Okuda, Hiroki Shimano, Satoshi Yamakawa, Masaki Tsukude, Kazutami Arimoto, Shinji Baba, Shinji Komori, Kazuo Kyuma, Akihiko Yasuoka, Haruhiko Abe
A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture. IEEE J. Solid State Circuits 31 (11) (1996)