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A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.

Narumi SakashitaFumihiro OkudaKen'ichi ShimomuraHiroki ShimanoMitsuhiro HamadaTetsuo TadaShinji KomoriKazuo KyumaAkihiko YasuokaHaruhiko Abe
Published in: ITC (1996)
Keyphrases
  • built in self test
  • low voltage
  • integrated circuit
  • high speed
  • main memory
  • high density
  • support vector
  • support vector machine
  • analog circuits