A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM.
Narumi SakashitaFumihiro OkudaKen'ichi ShimomuraHiroki ShimanoMitsuhiro HamadaTetsuo TadaShinji KomoriKazuo KyumaAkihiko YasuokaHaruhiko AbePublished in: ITC (1996)