On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC Platform.
Hiroki ShimanoFukashi MorishitaKatsumi DosakaKazutami ArimotoPublished in: IEICE Trans. Electron. (2009)
Keyphrases
- low power
- power dissipation
- power consumption
- high speed
- low cost
- high power
- single chip
- cmos technology
- nm technology
- mixed signal
- low power consumption
- ultra low power
- power reduction
- power management
- vlsi circuits
- logic circuits
- image sensor
- vlsi architecture
- energy efficiency
- digital signal processing
- power saving
- energy dissipation
- multithreading
- data center
- signal processor
- memory subsystem
- ibm power processor
- computational power
- embedded systems
- cmos image sensor
- low voltage
- image processing