A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture.
Narumi SakashitaYasuhiko NittaKen'ichi ShimomuraFumihiro OkudaHiroki ShimanoSatoshi YamakawaMasaki TsukudeKazutami ArimotoShinji BabaShinji KomoriKazuo KyumaAkihiko YasuokaHaruhiko AbePublished in: IEEE J. Solid State Circuits (1996)