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A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection.
Poki Chen
Joshua Adiel Wijaya
Seiji Kajihara
Trio Adiono
Hsiang-Yu Chen
Ruei-Ting Wang
Yousuke Miyake
Published in:
IEEE Access (2022)
Keyphrases
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low cost
data conversion
real time
computational complexity
single phase
high speed
variable sized
control system
signal processing
transfer function
image resolution