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Clock-Skew-Aware Scan Chain Grouping for Mitigating Shift Timing Failures in Low-Power Scan Testing.
Yucong Zhang
Xiaoqing Wen
Stefan Holst
Kohei Miyase
Seiji Kajihara
Hans-Joachim Wunderlich
Jun Qian
Published in:
ATS (2018)
Keyphrases
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low power
power consumption
high speed
low cost
logic circuits
high power
vlsi circuits
single chip
vlsi architecture
digital signal processing
low power consumption
power reduction
wireless transmission
real time
image sensor