Hiroshi Iwata

Publication Activity (10 Years)

Years Active: 2010-2017
Publications (10 Years): 1

Top Topics

Formal Verification

Top Venues

IEICE Trans. Inf. Syst.

Publications

Hiroshi Iwata, Nanami Katayama, Ken-ichi Yamaguchi
Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests. IEICE Trans. Inf. Syst. (6) (2017)
Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara
Test pattern selection to optimize delay test quality with a limited size of test set. ETS (2010)
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
Enabling False Path Identification from RTL for Reducing Design and Test Futileness. DELTA (2010)
Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara
A synthesis method to propagate false path information from RTL to gate level. DDECS (2010)
Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara
A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification. IEICE Trans. Inf. Syst. (7) (2010)
Takahiro Nomura, Hiroshi Iwata, Kohji Higuchi, Kazushi Nakano
Broadband robust PWM power amplifier using approximate 2DOF digital control. Artif. Life Robotics 15 (1) (2010)
Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara
Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits. Asian Test Symposium (2010)