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A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.

Hideo FujiwaraHiroyuki IwataTomokazu YonedaChia Yee Ooi
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2008)
Keyphrases
  • machine learning methods
  • statistical methods
  • probabilistic model
  • cost function
  • bayesian framework
  • user interface
  • high accuracy
  • model selection
  • clustering method
  • detection method