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Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique.
Alireza Monemi
Chia Yee Ooi
Muhammad Nadzir Marsono
Published in:
Int. J. Reconfigurable Comput. (2015)
Keyphrases
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network on chip
low latency
high speed
high throughput
real time
routing algorithm
highly efficient
network simulator
multi processor
stream processing
virtual machine
low power
power dissipation
orders of magnitude
microarray
operating system
interconnection networks