A Novel Scan Architecture for Low Power Scan-Based Testing.

Mahshid Mojtabavi Naeini Chia Yee Ooi

Published in: VLSI Design (2015)

Keyphrases

low power
power consumption
vlsi architecture
low cost
high speed
vlsi circuits
single chip
mixed signal
vlsi implementation
high power
nm technology
power reduction
logic circuits
low power consumption
delay insensitive
wireless transmission
cmos image sensor
low complexity
gate array