Rekha K. James

Publication Activity (10 Years)

Years Active: 2006-2023
Publications (10 Years): 16

Top Topics

Multi Processor

Network On Chip

Signaling Pathways

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

V. R. Josna, Rose George Kunthara, Rekha K. James, John Jose
Modelling and Impact Analysis of Push Back Attack in 3D Bufferless Network on Chip. MCSoC (2023)
K. Neethu, K. C. Sharin Shahana, Rekha K. James, John Jose, Sumit K. Mandal
ELEMENT: Energy-Efficient Multi-NoP Architecture for IMC-Based 2.5-D Accelerator for DNN Training. IEEE Des. Test 40 (6) (2023)
Rose George Kunthara, V. R. Josna, K. Neethu, Rekha K. James, John Jose
Modelling and Impact Analysis of Antipode Attack in Bufferless On-Chip Networks. SN Comput. Sci. 4 (3) (2023)
U. S. Shikha, Rekha K. James, Anju Pradeep, Sumi Baby, Jobymol Jacob
Threshold Voltage Modeling of Negative Capacitance Double Gate TFET. VLSID (2022)
Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
DAReS: Deflection Aware Rerouting between Subnetworks in Bufferless On-Chip Networks. ACM Great Lakes Symposium on VLSI (2022)
Akshay Sarman, Alwin Shaju, Rose George Kunthara, K. Neethu, Rekha K. James, John Jose
RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC. VLSI-SoC (2022)
Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
Traffic aware routing in 3D NoC using interleaved asymmetric edge routers. Nano Commun. Networks 27 (2021)
S. Sharon Dev, S. M. Krishna, S. S. Archana, Rose George Kunthara, K. Neethu, Rekha K. James
Dual Stage Encoding Technique to Minimize Cross Coupling across NoC Links. VDAT (2021)
Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, John Jose
DoLaR: Double Layer Routing for Bufferless Mesh Network-on-Chip. TENCON (2019)
Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
Asymmetric routing in 3D NoC using interleaved edge routers. NoCArc@MICRO (2019)
Rose George Kunthara, K. Neethu, Rekha K. James, Simi Zerine Sleeba, Tripti S. Warrier, John Jose
2L-2D Routing for Buffered Mesh Network-on-Chip. VDAT (2019)
Simi Zerine Sleeba, John Jose, Maurizio Palesi, Rekha K. James, Maniyelil Govindankutty Mini
Traffic Aware Deflection Rerouting Mechanism for Mesh Network on Chip. VLSI-SoC (2018)
Teresa K. George, K. Poulose Jacob, Rekha K. James
Token based Detection and Neural Network based Reconstruction framework against code injection vulnerabilities. J. Inf. Secur. Appl. 41 (2018)
Rose George Kunthara, Rekha K. James, Simi Zerine Sleeba, John Jose
ReDC: Reduced Deflection CHIPPER Router for Bufferless NoCs. ISED (2018)
C. K. Vijayakumari, Rekha K. James, P. Mythili
A GA Based Simple and Efficient Technique to Design Combinational Logic Circuits Using Universal Logic Modules. J. Circuits Syst. Comput. 25 (7) (2016)
Tuhin Subhra Chakraborty, Santanu Kundu, Deepak Agrawal, Sanjay Tanaji Shinde, Jacob Mathews, Rekha K. James
Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths. ACM Great Lakes Symposium on VLSI (2016)
Rekha K. James, K. Poulose Jacob, Sreela Sasi
High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA. NaBIC (2009)
Rekha K. James, K. Poulose Jacob, Sreela Sasi
Double Digit Decimal Multiplier on XILINX FPGA. ESA (2009)
Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi
RNS Based Programmable Multi-Mode Decimation Filter for WCDMA and WiMAX. VTC Spring (2008)
Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi
Fixed Point Decimal Multiplication Using RPS Algorithm. ISPA (2008)
Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi
Dual-mode RNS based programmable decimation filter for WCDMA and WLANa. ISCAS (2008)
Shahana Thottathikkulam Kassim, Babita R. Jose, Rekha K. James, K. Poulose Jacob, Sreela Sasi
RRNS-Convolutional encoded concatenated code for OFDM based wireless communication. ICON (2008)
Shahana Thottathikkulam Kassim, Rekha K. James, K. Poulose Jacob, Sreela Sasi
Genetic Algorithm-Based Combinational Logic Synthesis Using Universal Logic Modules. ESA (2007)
Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi
A New Look at Reversible Logic Implementation of Decimal Adder. SoC (2007)
Rekha K. James, Shahana Thottathikkulam Kassim, K. Poulose Jacob, Sreela Sasi
Delay-Reduced Combinational Logic Synthesis using Multiplexers. ESA (2006)