High Performance, Low Latency Double Digit Decimal Multiplier on ASIC and FPGA.
Rekha K. JamesK. Poulose JacobSreela SasiPublished in: NaBIC (2009)
Keyphrases
- low latency
- hardware implementation
- high speed
- hardware architecture
- field programmable gate array
- floating point
- high throughput
- xilinx virtex
- signal processing
- real time
- high bandwidth
- highly efficient
- single chip
- virtual machine
- efficient implementation
- massive scale
- low power
- stream processing
- general purpose
- end to end
- microarray
- mobile phone
- sensor networks
- database systems