A Reconfigurable Parallel Architecture for a Fuzzy Processor.
Giuseppe AsciaVincenzo CataniaAntonio PuliafitoLorenzo VitaPublished in: Inf. Sci. (1996)
Keyphrases
- parallel architecture
- systolic array
- hardware implementation
- parallel processing
- fuzzy sets
- shared memory
- distributed memory
- high level synthesis
- parallel implementation
- synthetic aperture sonar
- processing elements
- efficient implementation
- signal processing
- low cost
- neural network
- field programmable gate array
- hardware architecture
- pattern recognition
- computing systems
- data flow
- clock frequency
- special case